[AArch64] Used prefer aliases SXTL(2) and UXTL(2)

The SSHL and USHL instructions are used with a shift operand of zero to
sign and zero-extend integer vectors into wider modes.
GCC makes extensive use of them to "unpack" vectors.

AArch64 defines a shorthand alias for that case. Instead of writing:
SSHLL <Vd>.<Ta>, <Vn>.<Tb>, 0

we can write

SXTL <Vd>.<Ta>, <Vn>.<Tb>

Similar for the unsigned versions and the high-part versions (SSHL2 -> SXTL2).
This makes the assembly of vectorised functions a bit more readable.

	* config/aarch64/aarch64-simd.md
	(aarch64_simd_vec_unpack<su>_lo_<mode>): Use UXTL and SXTL assembler
	mnemonics.
	(aarch64_simd_vec_unpack<su>_hi_<mode>): Use UXTL2 and SXTL2 assembler
	mnemonics.

From-SVN: r261073

gcc/ChangeLog

+2018-06-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-simd.md
+	(aarch64_simd_vec_unpack<su>_lo_<mode>): Use UXTL and SXTL assembler
+	mnemonics.
+	(aarch64_simd_vec_unpack<su>_hi_<mode>): Use UXTL2 and SXTL2 assembler
+	mnemonics.
+
 2018-06-01  Richard Sandiford  <richard.sandiford@linaro.org>
 
 	PR tree-optimization/85989

gcc/config/aarch64/aarch64-simd.md

@@ -1492,7 +1492,7 @@
 			       (match_operand:VQW 2 "vect_par_cnst_lo_half" "")
 			    )))]
   "TARGET_SIMD"
-  "<su>shll\t%0.<Vwtype>, %1.<Vhalftype>, 0"
+  "<su>xtl\t%0.<Vwtype>, %1.<Vhalftype>"
   [(set_attr "type" "neon_shift_imm_long")]
 )
 
@@ -1503,7 +1503,7 @@
 			       (match_operand:VQW 2 "vect_par_cnst_hi_half" "")
 			    )))]
   "TARGET_SIMD"
-  "<su>shll2\t%0.<Vwtype>, %1.<Vtype>, 0"
+  "<su>xtl2\t%0.<Vwtype>, %1.<Vtype>"
   [(set_attr "type" "neon_shift_imm_long")]
 )