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Commit 76f93d99 by Segher Boessenkool Committed by Segher Boessenkool
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re PR target/64180 (PowerPC carry bit improvements) 

	PR target/64180
	* config/rs6000/darwin.md (macho_low_si): Remove "r" alternative.
	(macho_low_di): Ditto.
	* config/rs6000/rs6000.md (*largetoc_low): Ditto.
	(tocref<mode>): Ditto.
	(elf_low): Ditto.
	* config/rs6000/spe.md (mov_si<mode>_e500_subreg0_elf_low_be): Ditto.
	(mov_si<mode>_e500_subreg0_elf_low_le): Ditto.
	(mov_si<mode>_e500_subreg4_elf_low_be): Ditto.  Reformat condition.
	(mov_si<mode>_e500_subreg4_elf_low_le): Ditto.

From-SVN: r218590
parent 7b781771
Showing with 35 additions and 30 deletions
gcc/ChangeLog
2014-12-10 Segher Boessenkool <segher@kernel.crashing.org> 2014-12-10 Segher Boessenkool <segher@kernel.crashing.org>
PR target/64180 PR target/64180
* config/rs6000/darwin.md (macho_low_si): Remove "r" alternative.
(macho_low_di): Ditto.
* config/rs6000/rs6000.md (*largetoc_low): Ditto.
(tocref<mode>): Ditto.
(elf_low): Ditto.
* config/rs6000/spe.md (mov_si<mode>_e500_subreg0_elf_low_be): Ditto.
(mov_si<mode>_e500_subreg0_elf_low_le): Ditto.
(mov_si<mode>_e500_subreg4_elf_low_be): Ditto. Reformat condition.
(mov_si<mode>_e500_subreg4_elf_low_le): Ditto.
2014-12-10 Segher Boessenkool <segher@kernel.crashing.org>
PR target/64180
* config/rs6000/rs6000.c (TARGET_MD_ASM_CLOBBERS): Define. * config/rs6000/rs6000.c (TARGET_MD_ASM_CLOBBERS): Define.
(rs6000_md_asm_clobbers): New function. (rs6000_md_asm_clobbers): New function.
gcc/config/rs6000/darwin.md
...@@ -213,22 +213,18 @@ You should have received a copy of the GNU General Public License ...@@ -213,22 +213,18 @@ You should have received a copy of the GNU General Public License
}) })
(define_insn "macho_low_si" (define_insn "macho_low_si"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))] (match_operand 2 "" "")))]
"TARGET_MACHO && ! TARGET_64BIT" "TARGET_MACHO && ! TARGET_64BIT"
"@ "la %0,lo16(%2)(%1)")
la %0,lo16(%2)(%1)
addic %0,%1,lo16(%2)")
(define_insn "macho_low_di" (define_insn "macho_low_di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))] (match_operand 2 "" "")))]
"TARGET_MACHO && TARGET_64BIT" "TARGET_MACHO && TARGET_64BIT"
"@ "la %0,lo16(%2)(%1)")
la %0,lo16(%2)(%1)
addic %0,%1,lo16(%2)")
(define_split (define_split
[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "") [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
......
gcc/config/rs6000/rs6000.md
...@@ -10706,13 +10706,11 @@ ...@@ -10706,13 +10706,11 @@
"addis %0,%1+%3@u(%2)") "addis %0,%1+%3@u(%2)")
(define_insn "*largetoc_low" (define_insn "*largetoc_low"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand:DI 2 "" "")))] (match_operand:DI 2 "" "")))]
"TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
"@ "addi %0,%1,%2@l")
addi %0,%1,%2@l
addic %0,%1,%2@l")
(define_insn "*largetoc_low_aix<mode>" (define_insn "*largetoc_low_aix<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r") [(set (match_operand:P 0 "gpc_reg_operand" "=r")
...@@ -10722,7 +10720,7 @@ ...@@ -10722,7 +10720,7 @@
"la %0,%2@l(%1)") "la %0,%2@l(%1)")
(define_insn_and_split "*tocref<mode>" (define_insn_and_split "*tocref<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=b*r") [(set (match_operand:P 0 "gpc_reg_operand" "=b")
(match_operand:P 1 "small_toc_ref" "R"))] (match_operand:P 1 "small_toc_ref" "R"))]
"TARGET_TOC" "TARGET_TOC"
"la %0,%a1" "la %0,%a1"
...@@ -10741,13 +10739,11 @@ ...@@ -10741,13 +10739,11 @@
"lis %0,%1@ha") "lis %0,%1@ha")
(define_insn "elf_low" (define_insn "elf_low"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))] (match_operand 2 "" "")))]
"TARGET_ELF && ! TARGET_64BIT" "TARGET_ELF && ! TARGET_64BIT"
"@ "la %0,%2@l(%1)")
la %0,%2@l(%1)
addic %0,%1,%K2")
;; Call and call_value insns ;; Call and call_value insns
(define_expand "call" (define_expand "call"
......
gcc/config/rs6000/spe.md
...@@ -2519,7 +2519,7 @@ ...@@ -2519,7 +2519,7 @@
(define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low_be" (define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low_be"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0)
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))] (match_operand 2 "" "")))]
"WORDS_BIG_ENDIAN "WORDS_BIG_ENDIAN
&& (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
...@@ -2538,13 +2538,13 @@ ...@@ -2538,13 +2538,13 @@
(define_insn "*mov_si<mode>_e500_subreg0_elf_low_le" (define_insn "*mov_si<mode>_e500_subreg0_elf_low_le"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0)
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))] (match_operand 2 "" "")))]
"!WORDS_BIG_ENDIAN "!WORDS_BIG_ENDIAN
&& (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
|| (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)) || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
&& TARGET_ELF && !TARGET_64BIT)" && TARGET_ELF && !TARGET_64BIT)"
"addic %0,%1,%K2") "addi %0,%1,%K2")
;; ??? Could use evstwwe for memory stores in some cases, depending on ;; ??? Could use evstwwe for memory stores in some cases, depending on
;; the offset. ;; the offset.
...@@ -2592,17 +2592,17 @@ ...@@ -2592,17 +2592,17 @@
(define_insn "*mov_si<mode>_e500_subreg4_elf_low_be" (define_insn "*mov_si<mode>_e500_subreg4_elf_low_be"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4)
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))] (match_operand 2 "" "")))]
"WORDS_BIG_ENDIAN "WORDS_BIG_ENDIAN
&& (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
|| (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)) || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
&& TARGET_ELF && !TARGET_64BIT)" && TARGET_ELF && !TARGET_64BIT"
"addic %0,%1,%K2") "addi %0,%1,%K2")
(define_insn_and_split "*mov_si<mode>_e500_subreg4_elf_low_le" (define_insn_and_split "*mov_si<mode>_e500_subreg4_elf_low_le"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4)
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))] (match_operand 2 "" "")))]
"!WORDS_BIG_ENDIAN "!WORDS_BIG_ENDIAN
&& (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
......
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