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riscv-gcc-1
Commit 76ee8042 by Gavin Romig-Koch Committed by Gavin Romig-Koch
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mips.h (ISA_HAS_FP4,ISA_HAS_CONDMOVE,ISA_HAS_8CC): Split the second two from the first. 

	* config/mips/mips.h (ISA_HAS_FP4,ISA_HAS_CONDMOVE,ISA_HAS_8CC): Split
	the second two from the first.
	(CONDITIONAL_REGISTER_USAGE): Use ISA_HAS_8CC rather than ISA_HAS_FP4.
	* config/mips/mips.md (movcc,reload_incc,reload_outcc,
	conditional move): Use ISA_HAS_CONDMOVE or ISA_HAS_8CC rather than
	ISA_HAS_FP4.
	* config/mips/mips.c (mips_move_1word,gen_conditional_branch,
	override_options): Use ISA_HAS_CONDMOVE or ISA_HAS_8CC rather than
	ISA_HAS_FP4.

From-SVN: r30643
parent 1b8079e9
Showing with 51 additions and 26 deletions
gcc/ChangeLog
1999-11-23 Gavin Romig-Koch <gavin@cygnus.com>
* config/mips/mips.h (ISA_HAS_FP4,ISA_HAS_CONDMOVE,ISA_HAS_8CC): Split
the second two from the first.
(CONDITIONAL_REGISTER_USAGE): Use ISA_HAS_8CC rather than ISA_HAS_FP4.
* config/mips/mips.md (movcc,reload_incc,reload_outcc,
conditional move): Use ISA_HAS_CONDMOVE or ISA_HAS_8CC rather than
ISA_HAS_FP4.
* config/mips/mips.c (mips_move_1word,gen_conditional_branch,
override_options): Use ISA_HAS_CONDMOVE or ISA_HAS_8CC rather than
ISA_HAS_FP4.
Tue Nov 23 11:15:04 1999 Jeffrey A Law (law@cygnus.com)
* pa.md (call_internal_symref, call_value_internal_symref): No mode
......
gcc/config/mips/mips.c
......@@ -1719,7 +1719,7 @@ mips_move_1word (operands, insn, unsignedp)
ret = "mflo\t%0";
}
else if (ST_REG_P (regno1) && ISA_HAS_FP4)
else if (ST_REG_P (regno1) && ISA_HAS_8CC)
ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
else
......@@ -1728,7 +1728,7 @@ mips_move_1word (operands, insn, unsignedp)
if (FP_REG_P (regno1))
ret = "mfc1\t%0,%1";
else if (regno1 == FPSW_REGNUM && ! ISA_HAS_FP4)
else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
ret = "cfc1\t%0,$31";
}
}
......@@ -1755,7 +1755,7 @@ mips_move_1word (operands, insn, unsignedp)
}
}
else if (regno0 == FPSW_REGNUM && ! ISA_HAS_FP4)
else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
{
if (GP_REG_P (regno1))
{
......@@ -2873,7 +2873,7 @@ gen_conditional_branch (operands, test_code)
case CMP_SF:
case CMP_DF:
if (! ISA_HAS_FP4)
if (! ISA_HAS_8CC)
reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
else
reg = gen_reg_rtx (CCmode);
......@@ -4733,7 +4733,7 @@ override_options ()
if (mode == CCmode)
{
if (! ISA_HAS_FP4)
if (! ISA_HAS_8CC)
temp = (regno == FPSW_REGNUM);
else
temp = (ST_REG_P (regno) || GP_REG_P (regno)
......
gcc/config/mips/mips.h
......@@ -566,16 +566,29 @@ extern void sbss_section PARAMS ((void));
#define HAVE_SQRT_P() (mips_isa != 1)
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
#define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 || mips_isa == 64)
#define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
)
/* ISA has branch likely instructions (eg. mips2). */
#define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
/* ISA has the FP instructions introduced in mips4. */
#define ISA_HAS_FP4 (mips_isa == 4)
/* ISA has the conditional move instructions introduced in mips4. */
#define ISA_HAS_CONDMOVE (mips_isa == 4 \
)
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (mips_isa == 4 \
)
/* This is a catch all for the other new mips4 instructions: indexed load and
indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
and the FP recip and recip sqrt instructions */
#define ISA_HAS_FP4 (mips_isa == 4 \
)
/* ISA has the non-FP conditional move instructions introduced in mips4. */
#define ISA_HAS_CONDMOVE (mips_isa == 4)
/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
-mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
......@@ -645,7 +658,7 @@ do \
for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
else if (! ISA_HAS_FP4) \
else if (! ISA_HAS_8CC) \
{ \
int regno; \
\
......
gcc/config/mips/mips.md
......@@ -5565,7 +5565,7 @@ move\\t%0,%z4\\n\\
(define_insn "movcc"
[(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
(match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "SI")
......@@ -5577,7 +5577,7 @@ move\\t%0,%z4\\n\\
[(set (match_operand:CC 0 "register_operand" "=z")
(match_operand:CC 1 "general_operand" "z"))
(clobber (match_operand:TF 2 "register_operand" "=&f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
"
{
rtx source;
......@@ -5615,7 +5615,7 @@ move\\t%0,%z4\\n\\
[(set (match_operand:CC 0 "general_operand" "=z")
(match_operand:CC 1 "register_operand" "z"))
(clobber (match_operand:CC 2 "register_operand" "=&d"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
"
{
/* This is called when we are copying a condition code register out
......@@ -9955,7 +9955,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
......@@ -10001,7 +10001,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(const_int 0)])
(match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
......@@ -10016,7 +10016,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
......@@ -10031,7 +10031,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
......@@ -10047,7 +10047,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%T3.s\\t%0,%1,%4
mov%t3.s\\t%0,%2,%4"
......@@ -10062,7 +10062,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
......@@ -10077,7 +10077,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
......@@ -10093,7 +10093,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%T3.d\\t%0,%1,%4
mov%t3.d\\t%0,%2,%4"
......@@ -10108,7 +10108,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand" "")
(match_operand:SI 3 "reg_or_0_operand" "")))]
"ISA_HAS_CONDMOVE || ISA_HAS_FP4"
"ISA_HAS_CONDMOVE"
"
{
gen_conditional_move (operands);
......@@ -10121,7 +10121,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "se_reg_or_0_operand" "")
(match_operand:DI 3 "se_reg_or_0_operand" "")))]
"ISA_HAS_CONDMOVE || ISA_HAS_FP4"
"ISA_HAS_CONDMOVE"
"
{
gen_conditional_move (operands);
......@@ -10134,7 +10134,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(if_then_else:SF (match_dup 5)
(match_operand:SF 2 "register_operand" "")
(match_operand:SF 3 "register_operand" "")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"
{
gen_conditional_move (operands);
......@@ -10147,7 +10147,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
(if_then_else:DF (match_dup 5)
(match_operand:DF 2 "register_operand" "")
(match_operand:DF 3 "register_operand" "")))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
gen_conditional_move (operands);
......
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