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riscv-gcc-1
Commit 75fe7b2f by Richard Earnshaw Committed by Richard Earnshaw
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* arm.md (bunordered, bordered, bungt, bunlt, bunge, bunle, buneq) 

	(bltgt, arm_buneq, arm_bltgt, sunordered, sordered, sungt, sunge)
	(sunlt, sunle): Enable patterns on VFP.

	* arm.md (attribute 'type'): Add new types - f_loads floadd, f_stores,
	f_stored, f_flag, f_cvt.
	(generic_sched): No-longer used for the arm1020e and arm1022e cores.
	Include arm1020e.md.
	* vfp.md (fmstat): New cpu unit.  Add an exclusion set between it and
	the ds and fmac pipelines.  Re-work all load and store patterns and
	all conversion patterns to use new attributes.  Adjust reservation
	descriptions accordingly.
	* arm1020e.md: New file.
	* t-arm: Add dependency.

From-SVN: r100452
parent f7f7ac5a
Showing with 90 additions and 50 deletions
gcc/ChangeLog
2005-06-01 Richard Earnshaw <richard.earnshaw@arm.com>
* arm.md (bunordered, bordered, bungt, bunlt, bunge, bunle, buneq)
(bltgt, arm_buneq, arm_bltgt, sunordered, sordered, sungt, sunge)
(sunlt, sunle): Enable patterns on VFP.
* arm.md (attribute 'type'): Add new types - f_loads floadd, f_stores,
f_stored, f_flag, f_cvt.
(generic_sched): No-longer used for the arm1020e and arm1022e cores.
Include arm1020e.md.
* vfp.md (fmstat): New cpu unit. Add an exclusion set between it and
the ds and fmac pipelines. Re-work all load and store patterns and
all conversion patterns to use new attributes. Adjust reservation
descriptions accordingly.
* arm1020e.md: New file.
* t-arm: Add dependency.
2005-06-01 Jan Hubicka <jh@suse.cz>
* except.c (struct eh_region): Kill unused fields.
......
gcc/config/arm/arm.md
......@@ -202,10 +202,14 @@
; even on a machine with an fpa.
; f_load a floating point load from memory
; f_store a floating point store to memory
; f_load[sd] single/double load from memeory
; f_store[sd] single/double store to memeory
; f_flag a transfer of co-processor flags to the CPSR
; f_mem_r a transfer of a floating point register to a real reg via mem
; r_mem_f the reverse of f_mem_r
; f_2_r fast transfer float to arm (no memory needed)
; r_2_f fast transfer arm to float
; f_cvt convert floating<->integral
; branch a branch
; call a subroutine call
; load_byte load byte(s) from memory to arm registers
......@@ -222,7 +226,7 @@
; mav_dmult Double multiplies (7 cycle)
;
(define_attr "type"
"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult"
"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,f_flag,float_em,f_load,f_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult"
(if_then_else
(eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
(const_string "mult")
......@@ -313,12 +317,20 @@
(define_attr "generic_sched" "yes,no"
(const (if_then_else
(eq_attr "tune" "arm926ejs,arm1026ejs,arm1136js,arm1136jfs")
(eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs")
(const_string "no")
(const_string "yes"))))
(define_attr "generic_vfp" "yes,no"
(const (if_then_else
(and (eq_attr "fpu" "vfp")
(eq_attr "tune" "!arm1020e,arm1022e"))
(const_string "yes")
(const_string "no"))))
(include "arm-generic.md")
(include "arm926ejs.md")
(include "arm1020e.md")
(include "arm1026ejs.md")
(include "arm1136jfs.md")
......@@ -6963,7 +6975,7 @@
(if_then_else (unordered (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
arm_compare_op1);"
)
......@@ -6973,7 +6985,7 @@
(if_then_else (ordered (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
arm_compare_op1);"
)
......@@ -6983,7 +6995,7 @@
(if_then_else (ungt (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);"
)
......@@ -6992,7 +7004,7 @@
(if_then_else (unlt (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);"
)
......@@ -7001,7 +7013,7 @@
(if_then_else (unge (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);"
)
......@@ -7010,7 +7022,7 @@
(if_then_else (unle (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);"
)
......@@ -7021,7 +7033,7 @@
(if_then_else (uneq (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);"
)
......@@ -7030,7 +7042,7 @@
(if_then_else (ltgt (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);"
)
......@@ -7044,7 +7056,7 @@
(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"*
gcc_assert (!arm_ccfsm_state);
......@@ -7060,7 +7072,7 @@
(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"*
gcc_assert (!arm_ccfsm_state);
......@@ -7095,7 +7107,7 @@
(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"*
gcc_assert (!arm_ccfsm_state);
......@@ -7111,7 +7123,7 @@
(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"*
gcc_assert (!arm_ccfsm_state);
......@@ -7217,7 +7229,7 @@
(define_expand "sunordered"
[(set (match_operand:SI 0 "s_register_operand" "")
(unordered:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
arm_compare_op1);"
)
......@@ -7225,7 +7237,7 @@
(define_expand "sordered"
[(set (match_operand:SI 0 "s_register_operand" "")
(ordered:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
arm_compare_op1);"
)
......@@ -7233,7 +7245,7 @@
(define_expand "sungt"
[(set (match_operand:SI 0 "s_register_operand" "")
(ungt:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0,
arm_compare_op1);"
)
......@@ -7241,7 +7253,7 @@
(define_expand "sunge"
[(set (match_operand:SI 0 "s_register_operand" "")
(unge:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0,
arm_compare_op1);"
)
......@@ -7249,7 +7261,7 @@
(define_expand "sunlt"
[(set (match_operand:SI 0 "s_register_operand" "")
(unlt:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0,
arm_compare_op1);"
)
......@@ -7257,7 +7269,7 @@
(define_expand "sunle"
[(set (match_operand:SI 0 "s_register_operand" "")
(unle:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0,
arm_compare_op1);"
)
......@@ -7268,14 +7280,14 @@
; (define_expand "suneq"
; [(set (match_operand:SI 0 "s_register_operand" "")
; (uneq:SI (match_dup 1) (const_int 0)))]
; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
; "gcc_unreachable ();"
; )
;
; (define_expand "sltgt"
; [(set (match_operand:SI 0 "s_register_operand" "")
; (ltgt:SI (match_dup 1) (const_int 0)))]
; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
; "gcc_unreachable ();"
; )
......
gcc/config/arm/t-arm
......@@ -3,6 +3,7 @@
MD_INCLUDES= $(srcdir)/config/arm/arm-tune.md \
$(srcdir)/config/arm/predicates.md \
$(srcdir)/config/arm/arm-generic.md \
$(srcdir)/config/arm/arm1020e.md \
$(srcdir)/config/arm/arm1026ejs.md \
$(srcdir)/config/arm/arm1136jfs.md \
$(srcdir)/config/arm/arm926ejs.md \
......
gcc/config/arm/vfp.md
......@@ -55,53 +55,63 @@
(define_cpu_unit "vfp_ls" "vfp11")
(define_cpu_unit "fmstat" "vfp11")
(exclusion_set "fmac,ds" "fmstat")
;; The VFP "type" attributes differ from those used in the FPA model.
;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp.
;; farith Most arithmetic insns.
;; fmul Double precision multiply.
;; fdivs Single precision sqrt or division.
;; fdivd Double precision sqrt or division.
;; f_load Floating point load from memory.
;; f_store Floating point store to memory.
;; f_flag fmstat operation
;; f_load[sd] Floating point load from memory.
;; f_store[sd] Floating point store to memory.
;; f_2_r Transfer vfp to arm reg.
;; r_2_f Transfer arm to vfp reg.
;; f_cvt Convert floating<->integral
(define_insn_reservation "vfp_ffarith" 4
(and (eq_attr "fpu" "vfp")
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "ffarith"))
"fmac")
(define_insn_reservation "vfp_farith" 8
(and (eq_attr "fpu" "vfp")
(eq_attr "type" "farith"))
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "farith,f_cvt"))
"fmac")
(define_insn_reservation "vfp_fmul" 9
(and (eq_attr "fpu" "vfp")
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fmul"))
"fmac*2")
(define_insn_reservation "vfp_fdivs" 19
(and (eq_attr "fpu" "vfp")
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fdivs"))
"ds*15")
(define_insn_reservation "vfp_fdivd" 33
(and (eq_attr "fpu" "vfp")
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fdivd"))
"fmac+ds*29")
;; Moves to/from arm regs also use the load/store pipeline.
(define_insn_reservation "vfp_fload" 4
(and (eq_attr "fpu" "vfp")
(eq_attr "type" "f_load,r_2_f"))
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_loads,f_loadd,r_2_f"))
"vfp_ls")
(define_insn_reservation "vfp_fstore" 4
(and (eq_attr "fpu" "vfp")
(eq_attr "type" "f_load,f_2_r"))
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_stores,f_stored,f_2_r"))
"vfp_ls")
(define_insn_reservation "vfp_to_cpsr" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_flag"))
"fmstat,vfp_ls*3")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Insn pattern
......@@ -127,7 +137,7 @@
flds%?\\t%0, %1\\t%@ int
fsts%?\\t%1, %0\\t%@ int"
[(set_attr "predicable" "yes")
(set_attr "type" "*,*,load1,store1,r_2_f,f_2_r,ffarith,f_load,f_store")
(set_attr "type" "*,*,load1,store1,r_2_f,f_2_r,ffarith,f_loads,f_stores")
(set_attr "pool_range" "*,*,4096,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,4084,*,*,*,*,1008,*")]
)
......@@ -161,7 +171,7 @@
gcc_unreachable ();
}
"
[(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_load,f_store")
[(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_loadd,f_stored")
(set_attr "length" "8,8,8,4,4,4,4,4")
(set_attr "pool_range" "*,1020,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
......@@ -186,7 +196,7 @@
fcpys%?\\t%0, %1
mov%?\\t%0, %1\\t%@ float"
[(set_attr "predicable" "yes")
(set_attr "type" "r_2_f,f_2_r,ffarith,*,f_load,f_store,load1,store1")
(set_attr "type" "r_2_f,f_2_r,ffarith,*,f_loads,f_stores,load1,store1")
(set_attr "pool_range" "*,*,1020,*,4096,*,*,*")
(set_attr "neg_pool_range" "*,*,1008,*,4080,*,*,*")]
)
......@@ -221,7 +231,7 @@
}
}
"
[(set_attr "type" "r_2_f,f_2_r,ffarith,*,load2,store2,f_load,f_store")
[(set_attr "type" "r_2_f,f_2_r,ffarith,*,load2,store2,f_loadd,f_stored")
(set_attr "length" "4,4,8,8,4,4,4,8")
(set_attr "pool_range" "*,*,1020,*,1020,*,*,*")
(set_attr "neg_pool_range" "*,*,1008,*,1008,*,*,*")]
......@@ -572,7 +582,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"fcvtds%?\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
(define_insn "*truncdfsf2_vfp"
......@@ -581,7 +591,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"fcvtsd%?\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
(define_insn "*truncsisf2_vfp"
......@@ -590,7 +600,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"ftosizs%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
(define_insn "*truncsidf2_vfp"
......@@ -599,7 +609,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"ftosizd%?\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
......@@ -609,7 +619,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"ftouizs%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
(define_insn "fixuns_truncdfsi2"
......@@ -618,7 +628,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"ftouizd%?\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
......@@ -628,7 +638,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"fsitos%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
(define_insn "*floatsidf2_vfp"
......@@ -637,7 +647,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"fsitod%?\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
......@@ -647,7 +657,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"fuitos%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
(define_insn "floatunssidf2"
......@@ -656,7 +666,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"fuitod%?\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "f_cvt")]
)
......@@ -689,7 +699,7 @@
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"fmstat%?"
[(set_attr "conds" "set")
(set_attr "type" "ffarith")]
(set_attr "type" "f_flag")]
)
(define_insn_and_split "*cmpsf_split_vfp"
......@@ -813,7 +823,7 @@
UNSPEC_PUSH_MULT))])]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"* return vfp_output_fstmx (operands);"
[(set_attr "type" "f_store")]
[(set_attr "type" "f_stored")]
)
......
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