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lvzhengyang
riscv-gcc-1
Commits
75d39459
Commit
75d39459
authored
Jan 24, 1999
by
David Edelsohn
Committed by
Michael Meissner
Jan 24, 1999
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Fix problems found by David Edelsohn I caused
From-SVN: r24851
parent
081cc1f7
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Showing
2 changed files
with
28 additions
and
16 deletions
+28
-16
gcc/ChangeLog
+10
-2
gcc/config/rs6000/rs6000.md
+18
-14
No files found.
gcc/ChangeLog
View file @
75d39459
Sun
Jan
24
20
:
13
:
45
1999
David
Edelsohn
<
edelsohn
@mhpcc
.
edu
>
*
rs6000
.
md
(
left
shift
+
set
cr
patterns
)
:
Add
missing
'#'
to
split
patterns
.
(
move
register
+
set
cr
pattern
)
:
Ditto
.
*
rs6000
.
md
(
movdi
,
!
TARGET_POWERPC64
splitters
)
:
Add
back
in
Jan
.
15
th
patch
,
inadvertently
deleted
.
Sun
Jan
24
08
:
07
:
59
1999
Jeffrey
A
Law
(
law
@cygnus
.
com
)
*
stmt
.
c
(
stmt_loop_nest_empty
)
:
New
function
.
*
tree
.
h
(
stmt_loop_nest_empty
)
:
Declare
it
.
*
stmt
.
c
(
stmt_loop_nest_empty
)
:
New
function
.
*
tree
.
h
(
stmt_loop_nest_empty
)
:
Declare
it
.
*
rtl
.
def
(
CALL_PLACEHOLDER
)
:
New
rtx
code
.
Sun
Jan
24
21
:
24
:
43
1999
Michael
Hayes
<
m
.
hayes
@elec
.
canterbury
.
ac
.
nz
>
...
...
gcc/config/rs6000/rs6000.md
View file @
75d39459
...
...
@@ -4265,7 +4265,9 @@
(const_int 0)))
(clobber (match_scratch:SI 4 "=r,r"))]
"includes_lshift_p (operands
[
2
]
, operands
[
3
]
)"
"{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
"@
{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
#"
[
(set_attr "type" "delayed_compare")
]
)
(define_split
...
...
@@ -4296,7 +4298,9 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"includes_lshift_p (operands
[
2
]
, operands
[
3
]
)"
"{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
"@
{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
#"
[
(set_attr "type" "delayed_compare")
]
)
(define_split
...
...
@@ -8405,7 +8409,9 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
""
"mr. %0,%1"
"@
mr. %0,%1
#"
[
(set_attr "type" "compare")
]
)
(define_split
...
...
@@ -8992,13 +8998,18 @@
{
operands
[
2
]
= gen_rtx_SUBREG (SImode, operands
[
0
]
, WORDS_BIG_ENDIAN == 0);
operands
[
3
]
= gen_rtx_SUBREG (SImode, operands
[
0
]
, WORDS_BIG_ENDIAN != 0);
#if HOST_BITS_PER_WIDE_INT == 32
operands
[
4
]
= (INTVAL (operands
[
1
]
) & 0x80000000) ? constm1_rtx : const0_rtx;
#else
operands
[
4
]
= (HOST_WIDE_INT) INTVAL (operands
[
1
]
) >> 32;
operands
[
1
]
= INTVAL (operands
[
1
]
) & 0xffffffff;
#endif
}")
(define_split
[
(set (match_operand:DI 0 "gpc_reg_operand" "")
(match_operand:DI 1 "const_double_operand" ""))]
"! TARGET_POWERPC64 && reload_completed"
"
HOST_BITS_PER_WIDE_INT == 32 &&
! TARGET_POWERPC64 && reload_completed"
[
(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
"
...
...
@@ -9170,16 +9181,9 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
"TARGET_POWERPC64"
"mr. %0,%1"
[
(set_attr "type" "compare")
]
)
(define_insn ""
[
(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
""
"mr. %0,%1"
"@
mr. %0,%1
#"
[
(set_attr "type" "compare")
]
)
(define_split
...
...
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