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riscv-gcc-1
Commit 74eb5c52 by Doug Evans
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(emit_reload_insns): Record additional spill registers in their intrinsic mode. 

From-SVN: r7088
parent ca4aac00
Showing with 4 additions and 2 deletions
gcc/reload1.c
...@@ -6372,7 +6372,8 @@ emit_reload_insns (insn) ...@@ -6372,7 +6372,8 @@ emit_reload_insns (insn)
if (nregno < FIRST_PSEUDO_REGISTER) if (nregno < FIRST_PSEUDO_REGISTER)
for (k = 1; k < nnr; k++) for (k = 1; k < nnr; k++)
reg_last_reload_reg[nregno + k] reg_last_reload_reg[nregno + k]
= (nr == nnr ? gen_rtx (REG, word_mode, = (nr == nnr ? gen_rtx (REG,
reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
REGNO (reload_reg_rtx[r]) + k) REGNO (reload_reg_rtx[r]) + k)
: 0); : 0);
...@@ -6413,7 +6414,8 @@ emit_reload_insns (insn) ...@@ -6413,7 +6414,8 @@ emit_reload_insns (insn)
if (nregno < FIRST_PSEUDO_REGISTER) if (nregno < FIRST_PSEUDO_REGISTER)
for (k = 1; k < nnr; k++) for (k = 1; k < nnr; k++)
reg_last_reload_reg[nregno + k] reg_last_reload_reg[nregno + k]
= (nr == nnr ? gen_rtx (REG, word_mode, = (nr == nnr ? gen_rtx (REG,
reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
REGNO (reload_reg_rtx[r]) + k) REGNO (reload_reg_rtx[r]) + k)
: 0); : 0);
......
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