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Commit 73a4d10b by J"orn Rennecke Committed by Joern Rennecke
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly) 


gcc:

2005-05-09  J"orn Rennecke <joern.rennecke@st.com>

	* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
	if flag_signaling_nans is set.
	For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
	* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.

2005-05-06  J"orn Rennecke <joern.rennecke@st.com>
	Merge of sh-elf specific patches from sh-elf-4_1-branch:

	2005-05-05  Kaz Kojima  <kkojima@gcc.gnu.org>

	  * config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
	  (ASM_OUTPUT_REG_POP): Likewise.

	2005-05-05  J"orn Rennecke  <joern.rennecke@st.com>
		    Kaz Kojima  <kkojima@gcc.gnu.org>

	  * config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
	  and plus_constant.

	2005-05-04  Kaz Kojima  <kkojima@gcc.gnu.org>

	  * config/sh/sh.c (sh_div_strategy): Initialize with
	  SH_DIV_STRATEGY_DEFAULT.
	  * config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
	  (SH_DIV_STRATEGY_DEFAULT): Likewise.
	  (OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
	  when optimized for size.
	  * config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
	  (SH_DIV_STR_FOR_SIZE): Likewise.
	  * config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
	  (SH_DIV_STR_FOR_SIZE): Likewise.

	2005-05-04  J"orn Rennecke <joern.rennecke@st.com>

	  * config/sh/sh-modes.def (PDImode): Add.
	  * config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
	  * config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
	  (target_reg_operand): Allow PDImode.
	  (sh_register_move_cost): If neither sh_gettrcost_str nor
	  TARGET_PT_FIXED is set, assume gettr costs 100.
	  (shmedia_prepare_call_address): New function.
	  (sh_gettrcost_str): Initialize to empty string.
	  (sh_divsi3_libfunc): New variable.
	  * config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
	  (TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
	  (TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
	  (TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
	  TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
	  (TARGET_OPTIONS): Add -mdivsi3_libfunc.
	  (OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
	  by the user.
	  Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
	  (HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
	  (CONSTRAINT_LEN): Remove debug version.
	  (SECONDARY_INOUT_RELOAD_CLASS:) Break out of
	  (SECONDARY_OUTPUT_RELOAD_CLASS).  Use EXTRA_CONSTRAINT_Csy for check
	  if a target register needs a secondary reload through GENERAL_REGS.
	  (SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
	  (sh_divsi3_libfunc): Declare.
	  (FUNCTION_PROFILER): Provide SHMEDIA version.
	  * config/sh/predicates.md: New file.
	  * config/sh/sh.md (predicates.md): Include.
	  (divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
	  (reload_insi): Fix predicates and constraints.
	  (ptabs): New expander.
	  (*extendsipdi_media, *truncdipdi_media): New insns.
	  (call, call_value, sibcall): Use shmedia_prepare_call_address.
	  * doc/invoke.texi (-multcost, -mdiv): Document new SH options.
	  (-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
	  (-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.

	2005-04-11  J"orn Rennecke <joern.rennecke@st.com>

	  * sh.c (print_operand): Remove sh_rep_vec extraction.
	  (sh_output_mi_thunk): Make i unsigned.

	  * sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
	  (sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
	  is defined.  Update label detection code and iteration lookup,
	  enable basic functionality, but without IV analysis.

	2005-04-11  J"orn Rennecke <joern.rennecke@st.com>

	  * sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
	  flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
	  Set flag_finite_math_only to 2.
	  If flag_finite_math_only set set to 2, set it to 1 iff
	  we use SH2E..SH4 arithmetic without full IEEE support.

	2005-04-09  Kaz Kojima  <kkojima@gcc.gnu.org>

	  * config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
	  * config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.

	2005-04-06  J"orn Rennecke <joern.rennecke@st.com>

	  Merge of SuperH / STM SH specific patches, including fix for
	  PR target/20695:
	  * config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
	  when building with libgloss.
	  (sh*elf): Implement --without-fp option.
	  (sh64-superh-linux*): Don't multilib.
	  (sh*-*-linux): Use sh3 as basic multilib.
	  * config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
	  and to set up vbr.  Enable FPU before calling set_fpscr.
	  Load atexit address just before use.  Use __SH_FPU_ANY__.
	  (SH3*/SH4* start): Add code to set up vbr.  Use __SH_FPU_ANY__.
	  Set DN bit in fpscr.
	  * config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
	   config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
	  * config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
	  (FMOVD_WORKS): Don't define for __SH5__.
	  (ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
	  (ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
	  (ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
	  (ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
	  (ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
	  (ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
	  (ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
	  (ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
	  (ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
	  (movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
	  (movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
	  (movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
	  (movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
	  (movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
	  (movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
	  (movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
	  (movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
	  (movmemSI0, movstrSI0): Remove.
	  (movmemSI4): Schedule last store into rts delay slot.
	  (movmem): Shorten code.  Provide ENDFUNC.
	  (movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
	  (mulsi3): Provide ENDFUNC.
	  (sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
	  (SH5 sdivsi3): Reimplement, using:
	  (div_table): New, linear approximation table lookup for division seed.
	  (sdivsi3_2): New SH5 entry point.
	  (divdi3): Use hidden alias for udivdi3.
	  (moddi3): Use hidden alias for umoddi3.
	  (init_trampoline): Hide.  Provide exact ENDFUNC.
	  (ic_invalidate): Hide.  Re-implement SH4 version, using
	  (ic_invalidate_array): New global.
	  (GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
	  (GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
	  (GCC_pop_shmedia_regs_nofpu): Likewise.
	  * config/sh/libgcc-excl.ver (__mulsi3): Add.
	  * config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
	  * config/sh/sh-protos.h (sh_function_kind): New enum.
	  (sh_gen_truncate, replace_n_hard_rtx): Declare.
	  (function_symbol): Update declaration.
	  (shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
	  * sh.c (cfgloop.h): Include.
	  (TARGET_ADJUST_UNROLL_MAX): Redefine.
	  (print_operand): Add '>' and 'U' support.  Handle TRUNCATE and
	  SIGN_EXTEND.
	  (function_sybol): Add arguments for target and kind of symbol.
	  If not an ordinary function symbol, make sure the string becomes
	  unique.  For PIC, load appropriately depending on kind of symbol.
	  Changed all callers.
	  (prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
	  (multcosts): Check sh_multcost_str.  If not set, return 2 for
	  SHMEDIA TARGET_SMALLCODE.
	  (sh_rtx_costs): Lower some costs when outer_code is SET.  Add code
	  for CONST_VECTOR, MINUS and PARALLEL.
	  (gen_shifty_op): Don't emit nop.
	  (expand_ashiftrt): While expanding to rtl, do shift by 31 using a
	  register set to zero.
	  (gen_datalabel_ref): Make sure that the string is shared.
	  (MAX_POOL_SIZE): Define as 372.
	  (find_barrier): Remove spurious adjustment.
	  (sh_media_register_for_return): Return -1 for interrupt handlers.
	  (sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
	  (general_movsrc_operand): Accept vector that match sh_rep_vec.
	  (general_movdst_operand): For SHmedia, recject paradoxical DImode
	  subregs before high_life / reload.
	  (arith_reg_operand): Allow no-op sign extensions.
	  (logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
	  (cmp_operand, shift_operator, logical_operator): Likewise.
	  (minuend_operand, ua_address_operand, cache_address_operand): Likewise.
	  (ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
	  (sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
	  (shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
	  (sh_contains_memref_p): Likewise.
	  (shmedia_6bit_operand): Remove.
	  (arith_operand): Allow some TRUNCATEs.
	  (logical_operand): Disallow subregs <= SImode of >= DImode.
	  (greater_comparison_operator): Fix mode comparison.
	  (less_comparison_operator): Likewise.
	  (target_reg_operand, target_operand): Compare modes with Pmode.
	  (sh_adjust_cost): Consider the dependency between a target register
	  load and its use in a subsequent block.
	  Implement mac_media latency exception.
	  Before reload, anticipate floating point latencies to be at least four.
	  Give preference to the ptabs feeding a casesi_jump_media.
	  Handle UNSPEC in a CALL address.
	  (sh_optimize_target_register_callee_saved): Improve handling of
	  borderline cases.
	  (sh_function_ok_for_sibcall): Allow for non-pic, and also when we
	  will use the symbol with @GOTOFF addressing.
	  (SH_BLTIN_UDI): Remove.
	  (SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
	  (SH_BLTIN_STUA_Q64): Likewise.
	  (signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
	  (SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
	  (SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
	  (bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
	  {ld,st}{hi,lo}.[lq] and prefetch.
	  Change mextr entries to use SH_BLTIN_V8QI3.
	  (sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
	  TARGET_SHMEDIA64 checks for pointer arguments.
	  (sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
	  (sh_register_move_cost): Check sh_gettrcost_str.
	  (cmpsi_operand): T_REG is only allowed for TARGET_SH1.
	  (sh_output_mi_thunk): Make static.  Check that needed registers are
	  actually available.  Make sure that the sibcall won't go via the PLT.
	  (sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
	  (cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
	  (arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
	  * sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
	  __SH_FPU_DOUBLE__.
	  (INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
	  (TARGET_HARVARD): Also true for TARGET_SH5.
	  (TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
	  (TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
	  (TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
	  (TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
	  (TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
	  (TARGET_SWITCHES): Removed excessive whitespace.  Added options
	  indexed-addressing, no-indexed-addressing, adjust-unroll and
	  no-adjust-unroll.
	  (TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
	  (TARGET_OPTIONS): Define.
	  (EXTRA_SPECS): Add subtarget_asm_spec.
	  (SH_ASM_SPEC): Pass cut2-workaround option.
	  (SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
	  (LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
	  (OPTIMIZATION_OPTIONS): Set sh_div_str.  If not using if not -mieee,
	  set flag_finite_math_only.
	  (sh_divide_strategy_e): New enum.
	  (sh_div_strategy): Declare.
	  (OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
	  Clear flag_if_conversion2 for SHMEDIA.
	  Set sh_div_strategy.
	  Leave profile_flag and profile_arc_flag alone.
	  (LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
	  (HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
	  (MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
	  of the same size.
	  (CONST_OK_FOR_I): Fix detection of I06 constraint.
	  (PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
	  PIC_DIRECT_ADDR_P.
	  (SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses.  For TARGET_SHMEDIA,
	  check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
	  (FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode.  For
	  TARGET_SHMEDIA32, promote to SImode.
	  (EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
	  (DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
	  (DATALABEL_REF_P): Don't define.
	  (NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
	  a CONST.  Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
	  Allow a LABEL_REF in a sum.
	  (BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
	  (INDEX_REGISTER_RTX_P): Likewise.
	  (GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
	  load / store.
	  (ALLOW_INDEXED_ADDRESS): Define.
	  (GO_IF_LEGITIMATE_ADDRESS): Use it.
	  (TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
	  beyond to less than 64 bit.
	  (PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
	  (rtx_equal_function_value_matters): Don't declare.
	  (arith_reg_operand): Allow sign_extend.
	  (PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand.  Add
	  any_arith_reg_dest, cache_address_operand, cmp_operand,
	  fp_arith_reg_dest, logical_operator, logical_reg_operand,
	  minuend_operand, shift_count_operand, shift_count_reg_operand,
	  shift_operator, ua_address_operand, ua_offset, unary_float_operator,
	  xor_operand.  Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
	  Remove shmedia_6bit_operand.
	  (SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
	  and target_reg_operand.
	  (SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
	  (sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
	  (cut2_workaround_str): Declare.
	  (INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
	  (LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
	  Substitute INDEX_REG_CLASS with R0_REGS.
	  * sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
	  (UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
	  (UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
	  (Attribute "length"): jump_media has length 8 if
	  TARGET_SH5_CUT2_WORKAROUND is true.
	  ("highpart"): New attribute.
	  (cmpsi): Allow TARGET_SHMEDIA.
	  (cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
	  (cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
	  (cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
	  (*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
	  (movdicc_true+2, movsicc_false, movsicc_true): Likewise.
	  (movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
	  (*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
	  (addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
	  (*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
	  (divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
	  (divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
	  (divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
	  (*andsi3_media, andcsi3): Likewise.
	  (cmpeqdi_media): Use cmp_operand operand predicate.
	  (*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
	  (adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
	  (addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
	  (subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
	  (*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
	  (mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
	  (mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
	  (umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
	  (*subsi3_media): Make define_insn_and_split.  Use minuend_operand
	  operand predicate.
	  (subsi3): Don't force operand 1 into a register if it is a SUBREG.
	  (udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
	  (divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
	  (bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
	  (*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
	  (call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
	  (indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
	  (symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
	  (return_media_i, return_media): Likewise.
	  (udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
	  (divsi3_i1_media): Likewise.  Don't clobber R2 / R3 / TR1 / TR2.
	  (divsi3): Add support for division by multiplying with inverse.
	  (andsi3): Use logical_reg_operand predicate.  Add SHmedia support.
	  (iorsi3): Rename to:
	  (*iorsi3_compact).
	  (xorsi3): Rename to:
	  (*xorsi3_compact).
	  (iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
	  (*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
	  (ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
	  (*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
	  (ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
	  (movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
	  (*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
	  (bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
	  (cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
	  (ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
	  (*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
	  (*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
	  (*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
	  (ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
	  (alloca_i+1): Likewise.
	  (prefetch_media): Inhibit generator function generation.
	  (prefetch_i4): Likewise.  Also enable for TARGET_SHCOMPACT.
	  (*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
	  (*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
	  (rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
	  (ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
	  (*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
	  (ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
	  (ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
	  (lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
	  (lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
	  (ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
	  (negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
	  (*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
	  (zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
	  (extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
	  (movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
	  (movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
	  (movnegt+1, divsf3_i): Likewise.
	  (xordi3): Use xor_operand operand predicate.
	  (ashlsi3_media): Use shift_count_operand operand predicate.
	  (ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
	  (ashrdi3_media): Likewise.
	  (ashrsi2_31+1): Use mov_neg_si_t.
	  (lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
	  Make sure that either the destination is not a subreg, or that the
	  shift generates a sufficient number of sign bit copies.
	  (*loaddi_trunc): Use any_register_operand predicate.
	  (ic_invalidate_line_sh4a): Likewise.
	  (*zero_extendhisi2_media+1): Use simplify_gen_subreg.
	  (*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
	  (extendsidi2): Add fmov.sl alternative.
	  (load_ra): Add mode for operand 1.
	  (*movsi_media): Discourage the use of floating point registers.
	  Allow TRUNCATE.
	  (*movsi_media_nofpu): Ignore target register alternative for register
	  preferencing.  Allow TRUNCATE.
	  (movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
	  (*movqi_media): Use extend_reg_or_0_operand predicate.
	  (*movdi_media): Ignore target register alternative for register
	  preferencing.  Discourage the use of floating point registers.
	  (*movdi_media_nofpu): Ignore target register alternative for register
	  preferencing.
	  (movdi_const_16bit+1): If the source is subregged from SImode,
	  sign-extend highpart.  Use ext_dest_operand predicate.
	  (movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
	  (reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
	  (stuff_delay_slot): Add modes for operands 0 and 1.
	  (*beq_media_i, *bgt_media_i): Add '>' to output templates.
	  (*blt_media_i, jump_media): Likewise.
	  (beq, bne): Pass through SImode inputs, and I06 constants.
	  (bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
	  (bltu, bgeu, bleu): Likewise.
	  (GOTaddr2picreg): Don't call gen_datalabel_ref.
	  (ptrel): Rename to:
	  (ptrel_di).
	  (tls_global_dynamic, tls_local_dynamic): Add mode for call.
	  (seq): Properly support input modes other than DImode.
	  (slt, sle, sgt, sge,sne): Properly support SImode.
	  (addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
	  (mac_media) Enable generator function generation.
	  (fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
	  (fix_truncdfdi2): Likewise.
	  (movv8qi_i+3): Enable for CONST0_RTX too.
	  (movv2hi_i): Use add.l, not addz.l.
	  (ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
	  (lshrv4hi3): Likewise.
	  (ussubv8qi3): Allow zero for operand 1.
	  (prefetch): Allow any mode for operand 0.  Enable for SHCOMPACT.
	  Use force_reg.
	  * config/sh/shmedia.md: (shmedia): Remove automaton declaration.
	  (sh5inst_pipe, sh5fpu_pipe): New automatons.
	  (sh5issue): Use sh5inst_pipe.
	  (sh5fds): Use sh5fpu_pipe.
	  (shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
	  * config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
	  with always_inline Attribute.
	  * t-sh64 (LIB1ASMFUNCS): Add _div_table.
	  * config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
	  (sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
	  (sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
	  (sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
	  (sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
	  (sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
	  (sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
	  (sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
	  (sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
	  (sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
	  (sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
	  (sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
	  (sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
	  (sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
	  (sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
	  (sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
	  (sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
	  (sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
	  (sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
	  (sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
	  (sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
	  (sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
	  (sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
	  (sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
	  (sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
	  (sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
	  (sh_media_PREFO, sh_media_ALLOCO): Likewise.
	  (sh_media_FCOSA_S, sh_media_FSINA_S): New function.
	  (sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
	  (sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
	  (sh_media_CMVEQ): Use C code. Add attribute always_inline.
	  (sh_media_CMVNE): Likewise.
	  (sh_media_ADDZ_L): Use C code.
	  (sh_media_unaligned_LD_L): Use intrinsics directly.
	  (sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
	  (sh_media_unaligned_ST_Q): Likewise.
	  * config/sh/divtab.c: New file.

	2005-04-06  Andrew Stubbs <andrew.stubbs@superh.com>
		    J"orn Rennecke <joern.rennecke@superh.com>

	  * config/sh/superh64.h, config/sh/superh.h: New files.
	  * config/sh/newlib.h, config/sh/t-superh: Likewise.
	  * config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.

gcc/testsuite:

2005-05-06  J"orn Rennecke <joern.rennecke@st.com>

	* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.

	* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.

From-SVN: r99460
parent ae156f85
Showing with 649 additions and 21 deletions
gcc/config/sh/divtab.c 0 → 100644
/* Copyright (C) 2003 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
In addition to the permissions in the GNU General Public License, the
Free Software Foundation gives you unlimited permission to link the
compiled version of this file into combinations with other programs,
and to distribute those combinations without any restriction coming
from the use of this file. (The General Public License restrictions
do apply in other respects; for example, they cover modification of
the file, and distribution when not linked into a combine
executable.)
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* Calculate division table for SH5Media integer division
Contributed by Joern Rernnecke
joern.rennecke@superh.com */
#include <stdio.h>
#include <math.h>
#define BITS 5
#define N_ENTRIES (1 << BITS)
#define CUTOFF_BITS 20
#define BIAS (-330)
double max_defect = 0.;
double max_defect_x;
double min_defect = 1e9;
double min_defect_x;
double max_defect2 = 0.;
double max_defect2_x;
double min_defect2 = 0.;
double min_defect2_x;
double min_defect3 = 01e9;
double min_defect3_x;
int min_defect3_val;
double max_defect3 = 0.;
double max_defect3_x;
int max_defect3_val;
static double note_defect3 (int val, double d2, double y2d, double x)
{
int cutoff_val = val >> CUTOFF_BITS;
double cutoff;
double defect;
if (val < 0)
cutoff_val++;
cutoff = (cutoff_val * (1<<CUTOFF_BITS) - val) * y2d;
defect = cutoff + val * d2;
if (val < 0)
defect = - defect;
if (defect > max_defect3)
{
max_defect3 = defect;
max_defect3_x = x;
max_defect3_val = val;
}
if (defect < min_defect3)
{
min_defect3 = defect;
min_defect3_x = x;
min_defect3_val = val;
}
}
/* This function assumes 32 bit integers. */
static double
calc_defect (double x, int constant, int factor)
{
double y0 = (constant - (int) floor ((x * factor * 64.))) / 16384.;
double y1 = 2 * y0 -y0 * y0 * (x + BIAS / (1.*(1LL<<30)));
double y2d0, y2d;
int y2d1;
double d, d2;
y1 = floor (y1 * (1024 * 1024 * 1024)) / (1024 * 1024 * 1024);
d = y1 - 1 / x;
if (d > max_defect)
{
max_defect = d;
max_defect_x = x;
}
if (d < min_defect)
{
min_defect = d;
min_defect_x = x;
}
y2d0 = floor (y1 * x * (1LL << 60-16));
y2d1 = (int) (long long) y2d0;
y2d = - floor ((y1 - y0 / (1<<30-14)) * y2d1) / (1LL<<44);
d2 = y1 + y2d - 1/x;
if (d2 > max_defect2)
{
max_defect2 = d2;
max_defect2_x = x;
}
if (d2 < min_defect2)
{
min_defect2 = d2;
min_defect2_x = x;
}
/* zero times anything is trivially zero. */
note_defect3 ((1 << CUTOFF_BITS) - 1, d2, y2d, x);
note_defect3 (1 << CUTOFF_BITS, d2, y2d, x);
note_defect3 ((1U << 31) - (1 << CUTOFF_BITS), d2, y2d, x);
note_defect3 ((1U << 31) - 1, d2, y2d, x);
note_defect3 (-1, d2, y2d, x);
note_defect3 (-(1 << CUTOFF_BITS), d2, y2d, x);
note_defect3 ((1U << 31) - (1 << CUTOFF_BITS) + 1, d2, y2d, x);
note_defect3 (-(1U << 31), d2, y2d, x);
return d;
}
int
main ()
{
int i;
unsigned char factors[N_ENTRIES];
short constants[N_ENTRIES];
int steps = N_ENTRIES / 2;
double step = 1. / steps;
double eps30 = 1. / (1024 * 1024 * 1024);
for (i = 0; i < N_ENTRIES; i++)
{
double x_low = (i < steps ? 1. : -3.) + i * step;
double x_high = x_low + step - eps30;
double x_med;
int factor, constant;
double low_defect, med_defect, high_defect, max_defect;
factor = (1./x_low- 1./x_high) / step * 256. + 0.5;
if (factor == 256)
factor = 255;
factors[i] = factor;
/* Use minimum of error function for x_med. */
x_med = sqrt (256./factor);
if (x_low < 0)
x_med = - x_med;
low_defect = 1. / x_low + x_low * factor / 256.;
high_defect = 1. / x_high + x_high * factor / 256.;
med_defect = 1. / x_med + x_med * factor / 256.;
max_defect
= ((low_defect > high_defect) ^ (x_med < 0)) ? low_defect : high_defect;
constant = (med_defect + max_defect) * 0.5 * 16384. + 0.5;
if (constant < -32768 || constant > 32767)
abort ();
constants[i] = constant;
calc_defect (x_low, constant, factor);
calc_defect (x_med, constant, factor);
calc_defect (x_high, constant, factor);
}
printf ("/* This table has been generated by divtab.c .\n");
printf ("Defects for bias %d:\n", BIAS);
printf (" Max defect: %e at %e\n", max_defect, max_defect_x);
printf (" Min defect: %e at %e\n", min_defect, min_defect_x);
printf (" Max 2nd step defect: %e at %e\n", max_defect2, max_defect2_x);
printf (" Min 2nd step defect: %e at %e\n", min_defect2, min_defect2_x);
printf (" Max div defect: %e at %d:%e\n", max_defect3, max_defect3_val, max_defect3_x);
printf (" Min div defect: %e at %d:%e\n", min_defect3, min_defect3_val, min_defect3_x);
printf (" Defect at 1: %e\n",
calc_defect (1., constants[0], factors[0]));
printf (" Defect at -2: %e */\n",
calc_defect (-2., constants[steps], factors[steps]));
printf ("\t.section\t.rodata\n");
printf ("\t.balign 2\n");
printf ("/* negative division constants */\n");
for (i = steps; i < 2 * steps; i++)
printf ("\t.word\t%d\n", constants[i]);
printf ("/* negative division factors */\n");
for (i = steps; i < 2*steps; i++)
printf ("\t.byte\t%d\n", factors[i]);
printf ("\t.skip %d\n", steps);
printf ("\t.global GLOBAL(div_table):\n");
printf ("GLOBAL(div_table):\n");
printf ("\t.skip %d\n", steps);
printf ("/* positive division factors */\n");
for (i = 0; i < steps; i++)
printf ("\t.byte\t%d\n", factors[i]);
printf ("/* positive division constants */\n");
for (i = 0; i < steps; i++)
printf ("\t.word\t%d\n", constants[i]);
exit (0);
}
gcc/config/sh/elf.h
...@@ -57,14 +57,6 @@ Boston, MA 02111-1307, USA. */ ...@@ -57,14 +57,6 @@ Boston, MA 02111-1307, USA. */
/* Pass -ml and -mrelax to the assembler and linker. */ /* Pass -ml and -mrelax to the assembler and linker. */
#undef ASM_SPEC #undef ASM_SPEC
#define ASM_SPEC SH_ASM_SPEC #define ASM_SPEC SH_ASM_SPEC
#undef SUBTARGET_ASM_ISA_SPEC
#define SUBTARGET_ASM_ISA_SPEC "\
%{m2a:--isa=sh2a} \
%{m2a-single:--isa=sh2a} \
%{m2a-single-only:--isa=sh2a} \
%{m2a-nofpu:--isa=sh2a-nofpu} \
%{m5-compact*:--isa=SHcompact} %{m5-32media*:--isa=SHmedia --abi=32} \
%{m5-64media*:--isa=SHmedia --abi=64}" ASM_ISA_DEFAULT_SPEC
#undef LINK_SPEC #undef LINK_SPEC
#define LINK_SPEC SH_LINK_SPEC #define LINK_SPEC SH_LINK_SPEC
......
gcc/config/sh/libgcc-excl.ver
...@@ -3,5 +3,6 @@ ...@@ -3,5 +3,6 @@
__ashlsi3 __ashlsi3
__ashrsi3 __ashrsi3
__lshrsi3 __lshrsi3
__mulsi3 # this is an SH1-only symbol.
__udivsi3 __udivsi3
} }
gcc/config/sh/linux.h
...@@ -48,7 +48,8 @@ Boston, MA 02111-1307, USA. */ ...@@ -48,7 +48,8 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT #undef TARGET_DEFAULT
#define TARGET_DEFAULT \ #define TARGET_DEFAULT \
(TARGET_CPU_DEFAULT | USERMODE_BIT | TARGET_ENDIAN_DEFAULT) (TARGET_CPU_DEFAULT | USERMODE_BIT | TARGET_ENDIAN_DEFAULT \
| TARGET_OPT_DEFAULT)
#define TARGET_ASM_FILE_END file_end_indicate_exec_stack #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
...@@ -104,3 +105,10 @@ Boston, MA 02111-1307, USA. */ ...@@ -104,3 +105,10 @@ Boston, MA 02111-1307, USA. */
#undef DBX_REGISTER_NUMBER #undef DBX_REGISTER_NUMBER
#define DBX_REGISTER_NUMBER(REGNO) \ #define DBX_REGISTER_NUMBER(REGNO) \
((! TARGET_SH5 && (REGNO) == 16) ? 16 : SH_DBX_REGISTER_NUMBER (REGNO)) ((! TARGET_SH5 && (REGNO) == 16) ? 16 : SH_DBX_REGISTER_NUMBER (REGNO))
/* Since libgcc is compiled with -fpic for this target, we can't use
__sdivsi3_1 as the division strategy for -O0 and -Os. */
#undef SH_DIV_STRATEGY_DEFAULT
#define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL2
#undef SH_DIV_STR_FOR_SIZE
#define SH_DIV_STR_FOR_SIZE "call2"
gcc/config/sh/netbsd-elf.h
/* Definitions for SH running NetBSD using ELF /* Definitions for SH running NetBSD using ELF
Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc. Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
Contributed by Wasabi Systems, Inc. Contributed by Wasabi Systems, Inc.
This file is part of GCC. This file is part of GCC.
...@@ -109,3 +109,10 @@ do \ ...@@ -109,3 +109,10 @@ do \
} \ } \
} \ } \
while (0) while (0)
/* Since libgcc is compiled with -fpic for this target, we can't use
__sdivsi3_1 as the division strategy for -O0 and -Os. */
#undef SH_DIV_STRATEGY_DEFAULT
#define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL2
#undef SH_DIV_STR_FOR_SIZE
#define SH_DIV_STR_FOR_SIZE "call2"
gcc/config/sh/newlib.h 0 → 100644
/* Definitions of target machine for gcc for Super-H using sh-superh-elf.
Copyright (C) 2001 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* This header file is used when with_libgloss is enabled during gcc
configuration. */
#undef LIB_SPEC
#define LIB_SPEC "-lc -lgloss"
gcc/config/sh/predicates.md 0 → 100644
(define_predicate "trapping_target_operand"
(match_code "if_then_else")
{
rtx cond, mem, res, tar, and;
if (GET_MODE (op) != PDImode)
return 0;
cond = XEXP (op, 0);
mem = XEXP (op, 1);
res = XEXP (op, 2);
if (GET_CODE (mem) != MEM
|| (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
return 0;
tar = XEXP (res, 0);
if (!rtx_equal_p (XEXP (mem, 0), tar)
|| GET_MODE (tar) != Pmode)
return 0;
if (GET_CODE (cond) == CONST)
{
cond = XEXP (cond, 0);
if (!EXTRA_CONSTRAINT_Csy (tar))
return 0;
if (GET_CODE (tar) == CONST)
tar = XEXP (tar, 0);
}
else if (!arith_reg_operand (tar, VOIDmode)
&& ! EXTRA_CONSTRAINT_Csy (tar))
return 0;
if (GET_CODE (cond) != EQ)
return 0;
and = XEXP (cond, 0);
return (GET_CODE (and) == AND
&& rtx_equal_p (XEXP (and, 0), tar)
&& GET_CODE (XEXP (and, 1)) == CONST_INT
&& GET_CODE (XEXP (cond, 1)) == CONST_INT
&& INTVAL (XEXP (and, 1)) == 3
&& INTVAL (XEXP (cond, 1)) == 3);
})
gcc/config/sh/sh-modes.def
...@@ -20,6 +20,8 @@ Boston, MA 02111-1307, USA. */ ...@@ -20,6 +20,8 @@ Boston, MA 02111-1307, USA. */
/* The SH uses a partial integer mode to represent the FPSCR register. */ /* The SH uses a partial integer mode to represent the FPSCR register. */
PARTIAL_INT_MODE (SI); PARTIAL_INT_MODE (SI);
/* PDI mode is used to represent a function address in a target register. */
PARTIAL_INT_MODE (DI);
/* Vector modes. */ /* Vector modes. */
VECTOR_MODE (INT, QI, 2); /* V2QI */ VECTOR_MODE (INT, QI, 2); /* V2QI */
......
gcc/config/sh/sh-protos.h
...@@ -24,6 +24,19 @@ Boston, MA 02111-1307, USA. */ ...@@ -24,6 +24,19 @@ Boston, MA 02111-1307, USA. */
#ifndef GCC_SH_PROTOS_H #ifndef GCC_SH_PROTOS_H
#define GCC_SH_PROTOS_H #define GCC_SH_PROTOS_H
enum sh_function_kind {
/* A function with normal C ABI */
FUNCTION_ORDINARY,
/* A special function that guarantees that some otherwise call-clobbered
registers are not clobbered. These can't go through the SH5 resolver,
because it only saves argument passing registers. */
SFUNC_GOT,
/* A special function that should be linked statically. These are typically
smaller or not much larger than a PLT entry.
Some also have a non-standard ABI which precludes dynamic linking. */
SFUNC_STATIC
};
#ifdef RTX_CODE #ifdef RTX_CODE
extern rtx sh_fsca_sf2int (void); extern rtx sh_fsca_sf2int (void);
extern rtx sh_fsca_df2int (void); extern rtx sh_fsca_df2int (void);
...@@ -101,6 +114,7 @@ extern int sh_can_redirect_branch (rtx, rtx); ...@@ -101,6 +114,7 @@ extern int sh_can_redirect_branch (rtx, rtx);
extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx); extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx);
extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx); extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx);
extern int sh_expand_t_scc (enum rtx_code code, rtx target); extern int sh_expand_t_scc (enum rtx_code code, rtx target);
extern rtx sh_gen_truncate (enum machine_mode, rtx, int);
extern bool sh_vector_mode_supported_p (enum machine_mode); extern bool sh_vector_mode_supported_p (enum machine_mode);
#ifdef TREE_CODE #ifdef TREE_CODE
extern void sh_va_start (tree, rtx); extern void sh_va_start (tree, rtx);
...@@ -137,7 +151,7 @@ extern void fpscr_set_from_mem (int, HARD_REG_SET); ...@@ -137,7 +151,7 @@ extern void fpscr_set_from_mem (int, HARD_REG_SET);
extern void sh_pr_interrupt (struct cpp_reader *); extern void sh_pr_interrupt (struct cpp_reader *);
extern void sh_pr_trapa (struct cpp_reader *); extern void sh_pr_trapa (struct cpp_reader *);
extern void sh_pr_nosave_low_regs (struct cpp_reader *); extern void sh_pr_nosave_low_regs (struct cpp_reader *);
extern rtx function_symbol (const char *); extern rtx function_symbol (rtx, const char *, enum sh_function_kind);
extern rtx sh_get_pr_initial_val (void); extern rtx sh_get_pr_initial_val (void);
extern rtx sh_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int); extern rtx sh_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
...@@ -147,6 +161,12 @@ extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, signed ...@@ -147,6 +161,12 @@ extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, signed
extern const char *sh_pch_valid_p (const void *data_p, size_t sz); extern const char *sh_pch_valid_p (const void *data_p, size_t sz);
extern bool sh_promote_prototypes (tree); extern bool sh_promote_prototypes (tree);
extern rtx replace_n_hard_rtx (rtx, rtx *, int , int);
extern int shmedia_cleanup_truncate (rtx *, void *);
extern int sh_contains_memref_p (rtx);
extern rtx shmedia_prepare_call_address (rtx fnaddr, int is_sibcall);
#endif /* ! GCC_SH_PROTOS_H */ #endif /* ! GCC_SH_PROTOS_H */
#ifdef SYMBIAN #ifdef SYMBIAN
......
gcc/config/sh/sh.md
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/sh/shmedia.md
...@@ -25,9 +25,11 @@ ...@@ -25,9 +25,11 @@
;; the integer and multimedia unit (imu), the load/store unit (lsu), and ;; the integer and multimedia unit (imu), the load/store unit (lsu), and
;; the floating point unit (fpu). ;; the floating point unit (fpu).
(define_automaton "shmedia") (define_automaton "sh5inst_pipe, sh5fpu_pipe")
(define_cpu_unit "sh5issue,sh5fds" "shmedia") (define_cpu_unit "sh5issue" "sh5inst_pipe")
(define_cpu_unit "sh5fds" "sh5fpu_pipe")
;; Every instruction on SH-5 occupies the issue resource for at least one ;; Every instruction on SH-5 occupies the issue resource for at least one
;; cycle. ;; cycle.
...@@ -86,8 +88,8 @@ ...@@ -86,8 +88,8 @@
;; can continue to issue. ;; can continue to issue.
(define_insn_reservation "shmedia_fdiv" 19 (define_insn_reservation "shmedia_fdiv" 19
(and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media")) (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media"))
"sh5fds*19") "sh5issue+sh5fds,sh5fds*18")
(define_insn_reservation "shmedia_dfdiv" 35 (define_insn_reservation "shmedia_dfdiv" 35
(and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media")) (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media"))
"sh5fds*35") "sh5issue+sh5fds,sh5fds*34")
gcc/config/sh/sshmedia.h
...@@ -31,6 +31,9 @@ Boston, MA 02111-1307, USA. */ ...@@ -31,6 +31,9 @@ Boston, MA 02111-1307, USA. */
#define _SSHMEDIA_H #define _SSHMEDIA_H
#if __SHMEDIA__ #if __SHMEDIA__
__inline__ static unsigned long long sh_media_GETCON (unsigned int k)
__attribute__((always_inline));
__inline__ static __inline__ static
unsigned long long unsigned long long
sh_media_GETCON (unsigned int k) sh_media_GETCON (unsigned int k)
...@@ -40,6 +43,9 @@ sh_media_GETCON (unsigned int k) ...@@ -40,6 +43,9 @@ sh_media_GETCON (unsigned int k)
return res; return res;
} }
__inline__ static void sh_media_PUTCON (unsigned long long mm, unsigned int k)
__attribute__((always_inline));
__inline__ static __inline__ static
void void
sh_media_PUTCON (unsigned long long mm, unsigned int k) sh_media_PUTCON (unsigned long long mm, unsigned int k)
......
gcc/config/sh/superh.h 0 → 100644
/* Definitions of target machine for gcc for Super-H using sh-superh-elf.
Copyright (C) 2001 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* This header file is used when the vendor name is set to 'superh'.
It configures the compiler for SH4 only and switches the default
endianess to little (although big endian is still available).
It also configures the spec file to the default board configuration
but in such a way that it can be overriden by a boardspecs file
(using the -specs= option). This file is expected to disable the
defaults and provide options --defsym _start and --defsym _stack
which are required by the SuperH configuration of GNU ld.
This file is intended to overide sh.h */
#ifndef _SUPERH_H
#define _SUPERH_H
#endif
#undef TARGET_VERSION
#define TARGET_VERSION fprintf (stderr, " (SuperH SH special %s)", __DATE__);
/* We override TARGET_PROCESSOR_SWITCHES in order to remove all the unrequired cpu options
and add options for all the SuperH CPU variants:
-m4-100 is an alias for -m4.
-m4-200 is an alias for -m4.
-m4-400 is an alias for -m4-nofpu and passes -isa=sh4-nommu-nofpu to the assembler.
-m4-500 is an alias for -m4-nofpu and passes -isa=sh4-nofpu to the assembler. */
#undef TARGET_PROCESSOR_SWITCHES
#define TARGET_PROCESSOR_SWITCHES \
{"4-500", TARGET_NONE, "SH4 500 series (FPU-less)" }, \
{"4-500", SELECT_SH4_NOFPU, "" }, \
{"4-400", TARGET_NONE, "SH4 400 series (MMU/FPU-less)" }, \
{"4-400", SELECT_SH4_NOFPU, "" }, \
{"4-200-single-only", TARGET_NONE, "SH4 200 series with double = float (SH3e ABI)" }, \
{"4-200-single-only", SELECT_SH4_SINGLE_ONLY, "" }, \
{"4-200-single", TARGET_NONE, "SH4 200 series with single precision pervading" }, \
{"4-200-single", SELECT_SH4_SINGLE, "" }, \
{"4-200-nofpu", TARGET_NONE, "SH4 200 series using soft floating point" }, \
{"4-200-nofpu", SELECT_SH4_NOFPU, "" }, \
{"4-200", TARGET_NONE, "SH4 200 series" }, \
{"4-200", SELECT_SH4_NOFPU, "" }, \
{"4-100-single-only", TARGET_NONE, "SH4 100 series with double = float (SH3e ABI)" }, \
{"4-100-single-only", SELECT_SH4_SINGLE_ONLY, "" }, \
{"4-100-single", TARGET_NONE, "SH4 100 series with single precision pervading" }, \
{"4-100-single", SELECT_SH4_SINGLE, "" }, \
{"4-100-nofpu", TARGET_NONE, "SH4 100 series using soft floating point" }, \
{"4-100-nofpu", SELECT_SH4_NOFPU, "" }, \
{"4-100", TARGET_NONE, "SH4 100 series" }, \
{"4-100", SELECT_SH4_NOFPU, "" }, \
{"4-single-only", TARGET_NONE, "Generic SH4 with double = float (SH3e ABI)" }, \
{"4-single-only", SELECT_SH4_SINGLE_ONLY, "" }, \
{"4-single", TARGET_NONE, "Generic SH4 with single precision pervading" }, \
{"4-single", SELECT_SH4_SINGLE, "" }, \
{"4-nofpu", TARGET_NONE, "Generic SH4 using soft floating point" }, \
{"4-nofpu", SELECT_SH4_NOFPU, "" }, \
{"4", TARGET_NONE, "Generic SH4 (default)" }, \
{"4", SELECT_SH4, "" }
/* Provide the -mboard= option used by the boardspecs file */
#undef SUBTARGET_OPTIONS
#define SUBTARGET_OPTIONS \
{ "board=", &boardtype, "Board name [and momory region].", 0 }, \
{ "runtime=", &osruntime, "Runtime name.", 0 }, \
/* These are required by the mboard= option and runtime= option
and are defined in sh.c but are not used anywhere */
extern const char * boardtype;
extern const char * osruntime;
/* Override the linker spec strings to use the new emultation
The specstrings are concatenated as follows
LINK_EMUL_PREFIX.(''|'32'|'64'|LINK_DEFAULT_CPU_EMUL).SUBTARGET_LINK_EMUL_SUFFIX
*/
#undef LINK_EMUL_PREFIX
#undef SUBTARGET_LINK_EMUL_SUFFIX
#define LINK_EMUL_PREFIX "superh"
#define SUBTARGET_LINK_EMUL_SUFFIX ""
/* Add the SUBTARGET_LINK_SPEC to add the board and runtime support and
change the endianness */
#undef SUBTARGET_LINK_SPEC
#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
#define SUBTARGET_LINK_SPEC "%(board_link) %(ldruntime) %{ml|!mb:-EL}%{mb:-EB}"
#else
#define SUBTARGET_LINK_SPEC "%(board_link) %(ldruntime) %{ml:-EL}%{mb|!ml:-EB}"
#endif
/* This is used by the link spec if the boardspecs file is not used (for whatever reason).
If the boardspecs file overrides this then an alternative can be used. */
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
{ "board_link", "--defsym _start=0x1000 --defsym _stack=0x30000" }, \
{ "asruntime", "" }, \
{ "cppruntime", "-D__GDB_SIM__" }, \
{ "cc1runtime", "" }, \
{ "ldruntime", "" }, \
{ "libruntime", "-lc -lgloss" }
/* Set the SUBTARGET_CPP_SPEC to define __EMBEDDED_CROSS__ which has an effect
on newlib and provide the runtime support */
#undef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC \
"-D__EMBEDDED_CROSS__ %{m4-100*:-D__SH4_100__} %{m4-200*:-D__SH4_200__} %{m4-400:-D__SH4_400__} %{m4-500:-D__SH4_500__} \
%(cppruntime)"
/* Override the SUBTARGET_ASM_SPEC to add the runtime support */
#undef SUBTARGET_ASM_SPEC
#define SUBTARGET_ASM_SPEC "%{m4-100*|m4-200*:-isa=sh4} %{m4-400:-isa=sh4-nommu-nofpu} %{m4-500:-isa=sh4-nofpu} %(asruntime)"
/* Override the SUBTARGET_ASM_RELAX_SPEC so it doesn't interfere with the
runtime support by adding -isa=sh4 in the wrong place. */
#undef SUBTARGET_ASM_RELAX_SPEC
#define SUBTARGET_ASM_RELAX_SPEC "%{!m4-100*:%{!m4-200*:%{!m4-400:%{!m4-500:-isa=sh4}}}}"
/* Create the CC1_SPEC to add the runtime support */
#undef CC1_SPEC
#define CC1_SPEC "%(cc1runtime)"
#undef CC1PLUS_SPEC
#define CC1PLUS_SPEC "%(cc1runtime)"
/* Override the LIB_SPEC to add the runtime support */
#undef LIB_SPEC
#define LIB_SPEC "%{!shared:%{!symbolic:%(libruntime) -lc}} %{pg:-lprofile -lc}"
gcc/config/sh/superh64.h 0 → 100644
/*
Definitions of target machine for gcc for SuperH using target sh-superh-elf,
Copyright 2000 Free Software Foundation, Inc.
Contributed by Alexandre Oliva <aoliva@redhat.com>
Modified for SuperH by Richard Shann
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* This header file is used when the vendor name is set to 'superh'.
It configures the compiler for SH5 only and switches the default
endianess to little.
This file is intended to overide sh.h, superh.h and sh64.h (which
should have been included in that order) */
#ifndef _SUPERH_H
#error superh64.h should not be used without superh.h
#endif
/* We override TARGET_PROCESSOR_SWITCHES in order to remove all the unrequired cpu options */
#undef TARGET_PROCESSOR_SWITCHES
#define TARGET_PROCESSOR_SWITCHES \
{"5-64media", TARGET_NONE, "" }, \
{"5-64media", SELECT_SH5_64, "SH5 64-bit SHmedia code" }, \
{"5-64media-nofpu", TARGET_NONE, "" }, \
{"5-64media-nofpu", SELECT_SH5_64_NOFPU, "SH5 64-bit FPU-less SHmedia code" }, \
{"5-32media", TARGET_NONE, "" }, \
{"5-32media", SELECT_SH5_32, "SH5 32-bit SHmedia code" }, \
{"5-32media-nofpu", TARGET_NONE, "" }, \
{"5-32media-nofpu", SELECT_SH5_32_NOFPU, "SH5 32-bit FPU-less SHmedia code" }, \
{"5-compact", TARGET_NONE, "" }, \
{"5-compact", SELECT_SH5_COMPACT, "SH5 SHcompact code" }, \
{"5-compact-nofpu", TARGET_NONE, "" }, \
{"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "SH5 FPU-less SHcompact code" }
gcc/config/sh/t-linux
TARGET_LIBGCC2_CFLAGS = -fpic -DNO_FPSCR_VALUES TARGET_LIBGCC2_CFLAGS = -fpic -DNO_FPSCR_VALUES
LIB1ASMFUNCS_CACHE = _ic_invalidate LIB1ASMFUNCS_CACHE = _ic_invalidate _ic_invalidate_array
LIB2FUNCS_EXTRA= LIB2FUNCS_EXTRA=
......
gcc/config/sh/t-sh64
EXTRA_MULTILIB_PARTS= crt1.o crti.o crtn.o crtbegin.o crtend.o
LIB1ASMFUNCS = \ LIB1ASMFUNCS = \
_sdivsi3 _sdivsi3_i4 _udivsi3 _udivsi3_i4 _set_fpscr \ _sdivsi3 _sdivsi3_i4 _udivsi3 _udivsi3_i4 _set_fpscr \
_shcompact_call_trampoline _shcompact_return_trampoline \ _shcompact_call_trampoline _shcompact_return_trampoline \
_shcompact_incoming_args _ic_invalidate _nested_trampoline \ _shcompact_incoming_args _ic_invalidate _nested_trampoline \
_push_pop_shmedia_regs \ _push_pop_shmedia_regs \
_udivdi3 _divdi3 _umoddi3 _moddi3 _udivdi3 _divdi3 _umoddi3 _moddi3 _div_table
MULTILIB_CPU_DIRS= $(ML_sh1) $(ML_sh2e) $(ML_sh2) $(ML_sh3e) $(ML_sh3) $(ML_sh4_nofpu) $(ML_sh4_single_only) $(ML_sh4_single) $(ML_sh4) $(ML_sh5_32media:m5-32media/=media32) $(ML_sh5_32media_nofpu:m5-32media-nofpu/=nofpu/media32) $(ML_sh5_compact:m5-compact/=compact) $(ML_sh5_compact_nofpu:m5-compact-nofpu/=nofpu/compact) $(ML_sh5_64media:m5-64media/=media64) $(ML_sh5_64media_nofpu:m5-64media-nofpu/=nofpu/media64) MULTILIB_CPU_DIRS= $(ML_sh1) $(ML_sh2e) $(ML_sh2) $(ML_sh3e) $(ML_sh3) $(ML_sh4_nofpu) $(ML_sh4_single_only) $(ML_sh4_single) $(ML_sh4) $(ML_sh5_32media:m5-32media/=media32) $(ML_sh5_32media_nofpu:m5-32media-nofpu/=nofpu/media32) $(ML_sh5_compact:m5-compact/=compact) $(ML_sh5_compact_nofpu:m5-compact-nofpu/=nofpu/compact) $(ML_sh5_64media:m5-64media/=media64) $(ML_sh5_64media_nofpu:m5-64media-nofpu/=nofpu/media64)
......
gcc/config/sh/t-superh 0 → 100644
MULTILIB_OPTIONS= mb m4-nofpu/m4-single/m4-single-only
MULTILIB_DIRNAMES=
MULTILIB_MATCHES = m4=m4-100 m4-nofpu=m4-100-nofpu m4-single=m4-100-single m4-single-only=m4-100-single-only \
m4=m4-200 m4-nofpu=m4-200-nofpu m4-single=m4-200-single m4-single-only=m4-200-single-only \
m4-nofpu=m4-400 \
m4-nofpu=m4-500
gcc/doc/invoke.texi
...@@ -660,7 +660,10 @@ See RS/6000 and PowerPC Options. ...@@ -660,7 +660,10 @@ See RS/6000 and PowerPC Options.
-mb -ml -mdalign -mrelax @gol -mb -ml -mdalign -mrelax @gol
-mbigtable -mfmovd -mhitachi -mrenesas -mno-renesas -mnomacsave @gol -mbigtable -mfmovd -mhitachi -mrenesas -mno-renesas -mnomacsave @gol
-mieee -misize -mpadstruct -mspace @gol -mieee -misize -mpadstruct -mspace @gol
-mprefergot -musermode} -mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
-mdivsi3_libfunc=@var{name} @gol
-madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
-minvalid-symbols}
@emph{SPARC Options} @emph{SPARC Options}
@gccoptlist{-mcpu=@var{cpu-type} @gol @gccoptlist{-mcpu=@var{cpu-type} @gol
...@@ -11466,6 +11469,11 @@ Mark the @code{MAC} register as call-clobbered, even if ...@@ -11466,6 +11469,11 @@ Mark the @code{MAC} register as call-clobbered, even if
@item -mieee @item -mieee
@opindex mieee @opindex mieee
Increase IEEE-compliance of floating-point code. Increase IEEE-compliance of floating-point code.
At the moment, this is equivalent to @option{-fno-finite-math-only}.
When generating 16 bit SH opcodes, getting IEEE-conforming results for
comparisons of NANs / infinities incurs extra overhead in every
floating point comparison, therefore the default is set to
@option{-ffinite-math-only}.
@item -misize @item -misize
@opindex misize @opindex misize
...@@ -11491,6 +11499,107 @@ Generate a library function call to invalidate instruction cache ...@@ -11491,6 +11499,107 @@ Generate a library function call to invalidate instruction cache
entries, after fixing up a trampoline. This library function call entries, after fixing up a trampoline. This library function call
doesn't assume it can write to the whole memory address space. This doesn't assume it can write to the whole memory address space. This
is the default when the target is @code{sh-*-linux*}. is the default when the target is @code{sh-*-linux*}.
@item -multcost=@var{number}
@opindex multcost=@var{number}
Set the cost to assume for a multiply insn.
@item -mdiv=@var{strategy}
@opindex mdiv=@var{strategy}
Set the division strategy to use for SHmedia code. @var{strategy} must be
one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call,
inv:call2, inv:fp .
"fp" performs the operation in floating point. This has a very high latency,
but needs only a few instructions, so it might be a good choice if
your code has enough easily esploitable ILP to allow the compiler to
schedule the floating point instructions together with other instructions.
Division by zero causes a floating point exception.
"inv" uses integer operations to calculate the inverse of the divisor,
and then multiplies the divident with the inverse. This strategy allows
cse and hoisting of the inverse calculation. Division by zero calculates
an unspecified result, but does not trap.
"inv:minlat" is a variant of "inv" where if no cse / hoisting opportunities
have been found, or if the entire operation has been hoisted to the same
place, the last stages of the inverse calculation are intertwined with the
final multiply to reduce the overall latency, at the expense of using a few
more instructions, and thus offering fewer scheduling opportunities with
other code.
"call" calls a library function that usually implements the inv:minlat
strategy.
This gives high code density for m5-*media-nofpu compilations.
"call2" uses a different entry point of the same library function, where it
assumes that a pointer to a lookup table has already been set up, which
exposes the pointer load to cse / code hoisting optimizations.
"inv:call", "inv:call2" and "inv:fp" all use the "inv" algorithm for initial
code generation, but if the code stays unoptimized, revert to the "call",
"call2", or "fp" strategies, resspectively. Note that the
potentially-trapping side effect of division by zero is carried by a
separate instruction, so it is possible that all the integer instructions
are hoisted out, but the marker for the side effect stays where it is.
A recombination to fp operations or a call is not possible in that case.
"inv20u" and "inv20l" are variants of the "inv:minlat" strategy. In the case
that the inverse calculation was nor separated from the multiply, they speed
up division where the dividend fits into 20 bits (plus sign where applicable),
by inserting a test to skip a number of operations in this case; this test
slows down the case of larger divdends. inv20u assumes the case of a such
a small dividend to be unlikely, and inv20l assumes it to be likely.
@item -mdivsi3_libfunc=@var{name}
@opindex mdivsi3_libfunc=@var{name}
Set the name of the library function used for 32 bit signed division to
@var{name}. This only affect the name used in the call and inv:call
division strategies, and the compiler will still expect the same
sets of input/output/clobbered registers as if this option was not present.
@item -madjust-unroll
@opindex madjust-unroll
Throttle unrolling to avoid thrashing target registers.
This option only has an effect if the gcc code base supports the
TARGET_ADJUST_UNROLL_MAX target hook.
@item -mindexed-addressing
@opindex mindexed-addressing
Enable the use of the indexed addressing mode for SHmedia32/SHcompact.
This is only safe if the hardware and/or OS implement 32 bit wrap-around
semantics for the indexed addressing mode. The architecture allows the
implementation of processors with 64 bit MMU, which the OS could use to
get 32 bit addressing, but since no current harware implementation supports
this or any other way to make the indexed addressing mode safe to use in
the 32 bit ABI, the default is -mno-indexed-addressing.
@item -mgettrcost=@var{number}
@opindex mgettrcost=@var{number}
Set the cost assumed for the gettr instruction to @var{number}.
The default is 2 if @option{-mpt-fixed} is in effect, 100 otherwise.
@item -mpt-fixed
@opindex mpt-fixed
Assume pt* instructions won't trap. This will generally generate better
scheduled code, but is unsafe on current hardware. The current architecture
definition says that ptabs and ptrel trap when the target anded with 3 is 3.
This has the unintentional effect of making it unsafe to schedule ptabs /
ptrel before a branch, or hoist it out of a loop. For example,
__do_global_ctors, a part of libgcc that runs constructors at program
startup, calls functions in a list which is delimited by -1. With the
-mpt-fixed option, the ptabs will be done before testing against -1.
That means that all the constructors will be run a bit quicker, but when
the loop comes to the end of the list, the pprogram crashes because ptabs
loads -1 into a target register. Since this option is unsafe for any
hardware implementing the current architecture specification, the default
is -mno-pt-fixed. Unless the user specifies a specific cost with
@option{-mgettrcost}, -mno-pt-fixed also implies @option{-mgettrcost=100};
this deters register allocation using target registers for storing
ordinary integers.
@item -minvalid-symbols
@opindex minvalid-symbols
Assume symbols might be invalid. Ordinary function symbols generated by
the compiler will always be valid to load with movi/shori/ptabs or
movi/shori/ptrel, but with assembler and/or linker tricks it is possible
to generate symbols that will cause ptabs / ptrel to trap.
This option is only meaningful when @option{-mno-pt-fixed} is in effect.
It will then prevent cross-basic-block cse, hoisting and most scheduling
of symbol loads. The default is @option{-mno-invalid-symbols}.
@end table @end table
@node SPARC Options @node SPARC Options
......
gcc/testsuite/ChangeLog
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
2005-05-09 Nathan Sidwell <nathan@codesourcery.com> 2005-05-09 Nathan Sidwell <nathan@codesourcery.com>
PR c++/21427 PR c++/21427
......
gcc/testsuite/gcc.dg/20021029-1.c
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
variables into writable sections. */ variables into writable sections. */
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-options "-O2 -fpic" } */ /* { dg-options "-O2 -fpic" } */
/* { dg-options "-O2 -fpic -mpt-fixed" { target sh64*-*-* } } */
/* { dg-final { scan-assembler-not ".data.rel.ro.local" } } */ /* { dg-final { scan-assembler-not ".data.rel.ro.local" } } */
int foo (int a) int foo (int a)
......
gcc/testsuite/gcc.dg/pr15784-3.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-options "-fdump-tree-generic" } */ /* SH4 without -mieee defaults to -ffinite-math-only. */
/* { dg-options "-fdump-tree-generic -fno-finite-math-only" } */
/* Test for folding abs(x) where appropriate. */ /* Test for folding abs(x) where appropriate. */
#define abs(x) x > 0 ? x : -x #define abs(x) x > 0 ? x : -x
extern double fabs (double); extern double fabs (double);
......
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