re PR target/19518 ([alpha] unrecognizable insn (set (reg:V4HI) (const_vector:V4HI)) with builtins)

        PR target/19518
        * config/alpha/alpha.c (alpha_rtx_costs): Handle HIGH.
        (alpha_preferred_reload_class): Handle CONST_VECTOR.
        (alpha_emit_set_const_1): Add no_output parameter; don't emit
        rtl if true.
        (alpha_emit_set_const): Likewise.  Make static.
        (alpha_emit_set_long_const): Make static.
        (alpha_extract_integer): Split out from alpha_expand_mov.
        (alpha_split_const_mov): Likewise.
        (alpha_expand_mov): Use them.  Handle CONST_VECTOR.
        (alpha_legitimate_constant_p): New.
        * config/alpha/alpha-protos.h: Update.
        * config/alpha/alpha.h (REGISTER_MOVE_COST): Correct fp<->gp cost.
        (LEGITIMATE_CONSTANT_P): Re-implement with a function.
        * config/alpha/alpha.md (movsi): Add n alternative.
        (movsi_nt_vms, movdi_er_nofix, movdi_er_fix, movdi_fix): Likewise.
        (mov<VEC>_fix, mov<VEC>_nofix): Add i alternative.
        (splitters for all of the above): Use alpha_split_const_mov.
        * config/alpha/predicates.md (non_add_const_operand): New.
        (non_zero_const_operand): New.
        (input_operand): Use alpha_legitimate_constant_p after reload.

From-SVN: r93943

gcc/ChangeLog

+2005-01-19  Richard Henderson  <rth@redhat.com>
+
+	PR target/19518
+	* config/alpha/alpha.c (alpha_rtx_costs): Handle HIGH.
+	(alpha_preferred_reload_class): Handle CONST_VECTOR.
+	(alpha_emit_set_const_1): Add no_output parameter; don't emit
+	rtl if true.
+	(alpha_emit_set_const): Likewise.  Make static.
+	(alpha_emit_set_long_const): Make static.
+	(alpha_extract_integer): Split out from alpha_expand_mov.
+	(alpha_split_const_mov): Likewise.
+	(alpha_expand_mov): Use them.  Handle CONST_VECTOR.
+	(alpha_legitimate_constant_p): New.
+	* config/alpha/alpha-protos.h: Update.
+	* config/alpha/alpha.h (REGISTER_MOVE_COST): Correct fp<->gp cost.
+	(LEGITIMATE_CONSTANT_P): Re-implement with a function.
+	* config/alpha/alpha.md (movsi): Add n alternative.
+	(movsi_nt_vms, movdi_er_nofix, movdi_er_fix, movdi_fix): Likewise.
+	(mov<VEC>_fix, mov<VEC>_nofix): Add i alternative.
+	(splitters for all of the above): Use alpha_split_const_mov.
+	* config/alpha/predicates.md (non_add_const_operand): New.
+	(non_zero_const_operand): New.
+	(input_operand): Use alpha_legitimate_constant_p after reload.
+
 2005-01-19  Zdenek Dvorak  <dvorakz@suse.cz>
 
 	PR tree-optimization/19038

gcc/config/alpha/alpha-protos.h

@@ -42,6 +42,7 @@ extern bool alpha_extra_constraint (rtx, int);
 extern rtx alpha_tablejump_addr_vec (rtx);
 extern rtx alpha_tablejump_best_label (rtx);
 
+extern bool alpha_legitimate_constant_p (rtx);
 extern bool alpha_legitimate_address_p (enum machine_mode, rtx, int);
 extern rtx alpha_legitimize_address (rtx, rtx, enum machine_mode);
 extern rtx alpha_legitimize_reload_address (rtx, enum machine_mode,
@@ -56,8 +57,7 @@ extern enum reg_class secondary_reload_class (enum reg_class,
 					      enum machine_mode, rtx, int);
 
 extern void alpha_set_memflags (rtx, rtx);
-extern rtx alpha_emit_set_const (rtx, enum machine_mode, HOST_WIDE_INT, int);
-extern rtx alpha_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+extern bool alpha_split_const_mov (enum machine_mode, rtx *);
 extern bool alpha_expand_mov (enum machine_mode, rtx *);
 extern bool alpha_expand_mov_nobwx (enum machine_mode, rtx *);
 extern void alpha_expand_movmisalign (enum machine_mode, rtx *);

gcc/config/alpha/alpha.h

@@ -884,10 +884,10 @@ enum reg_class {
    reduce the impact of not being able to allocate a pseudo to a
    hard register.  */
 
-#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)	\
-  (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS)	\
-   ? 2							\
-   : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
+#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)		\
+  (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS)	? 2	\
+   : TARGET_FIX ? ((CLASS1) == FLOAT_REGS ? 6 : 8)		\
+   : 4+2*alpha_memory_latency)
 
 /* A C expressions returning the cost of moving data of MODE from a register to
    or from memory.
@@ -1213,9 +1213,7 @@ do {						\
 /* Include all constant integers and constant doubles, but not
    floating-point, except for floating-point zero.  */
 
-#define LEGITIMATE_CONSTANT_P(X)  		\
-  (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT	\
-   || (X) == CONST0_RTX (GET_MODE (X)))
+#define LEGITIMATE_CONSTANT_P  alpha_legitimate_constant_p
 
 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
    and check its validity for a certain class.

gcc/config/alpha/alpha.md

@@ -5128,8 +5128,8 @@
 })
 
 (define_insn "*movsi"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m")
-	(match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
+	(match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
   "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
    && (register_operand (operands[0], SImode)
        || reg_or_0_operand (operands[1], SImode))"
@@ -5137,13 +5137,14 @@
    bis $31,%r1,%0
    lda %0,%1($31)
    ldah %0,%h1($31)
+   #
    ldl %0,%1
    stl %r1,%0"
-  [(set_attr "type" "ilog,iadd,iadd,ild,ist")])
+  [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
 
 (define_insn "*movsi_nt_vms"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
-	(match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
+	(match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
   "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
     && (register_operand (operands[0], SImode)
         || reg_or_0_operand (operands[1], SImode))"
@@ -5152,9 +5153,10 @@
    lda %0,%1
    ldah %0,%h1
    lda %0,%1
+   #
    ldl %0,%1
    stl %r1,%0"
-  [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist")])
+  [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
 
 (define_insn "*movhi_nobwx"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -5221,15 +5223,11 @@
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
-	(match_operand:SI 1 "const_int_operand" ""))]
-  "! add_operand (operands[1], SImode)"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
+	(match_operand:SI 1 "non_add_const_operand" ""))]
+  ""
+  [(const_int 0)]
 {
-  rtx tem
-    = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
-
-  if (tem == operands[0])
+  if (alpha_split_const_mov (SImode, operands))
     DONE;
   else
     FAIL;
@@ -5452,8 +5450,8 @@
 })
 
 (define_insn "*movdi_er_nofix"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
-	(match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
+	(match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
   "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
@@ -5463,21 +5461,22 @@
    ldah %0,%h1($31)
    #
    #
+   #
    ldq%A1 %0,%1
    stq%A0 %r1,%0
    fmov %R1,%0
    ldt %0,%1
    stt %R1,%0"
-  [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")
-   (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*")])
+  [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
+   (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
 
 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
 ;; have been split up by the rules above but we shouldn't reject the
 ;; possibility of them getting through.
 
 (define_insn "*movdi_nofix"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
-	(match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
+	(match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
   "! TARGET_FIX
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
@@ -5487,19 +5486,20 @@
    ldah %0,%h1($31)
    laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
    lda %0,%1
+   #
    ldq%A1 %0,%1
    stq%A0 %r1,%0
    cpys %R1,%R1,%0
    ldt %0,%1
    stt %R1,%0"
-  [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
-   (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
+  [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
+   (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
 
 (define_insn "*movdi_er_fix"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-				"=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
+				"=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
 	(match_operand:DI 1 "input_operand"
-				"rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
+				"rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
   "TARGET_EXPLICIT_RELOCS && TARGET_FIX
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
@@ -5509,6 +5509,7 @@
    ldah %0,%h1($31)
    #
    #
+   #
    ldq%A1 %0,%1
    stq%A0 %r1,%0
    fmov %R1,%0
@@ -5516,12 +5517,12 @@
    stt %R1,%0
    ftoit %1,%0
    itoft %1,%0"
-  [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")
-   (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*")])
+  [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
+   (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
 
 (define_insn "*movdi_fix"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
-	(match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
+	(match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
   "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
@@ -5530,6 +5531,7 @@
    lda %0,%1($31)
    ldah %0,%h1($31)
    lda %0,%1
+   #
    ldq%A1 %0,%1
    stq%A0 %r1,%0
    cpys %R1,%R1,%0
@@ -5537,7 +5539,7 @@
    stt %R1,%0
    ftoit %1,%0
    itoft %1,%0"
-  [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
+  [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
 
 ;; VMS needs to set up "vms_base_regno" for unwinding.  This move
 ;; often appears dead to the life analysis code, at which point we
@@ -5568,15 +5570,11 @@
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
-	(match_operand:DI 1 "const_int_operand" ""))]
-  "! add_operand (operands[1], DImode)"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
+	(match_operand:DI 1 "non_add_const_operand" ""))]
+  ""
+  [(const_int 0)]
 {
-  rtx tem
-    = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
-
-  if (tem == operands[0])
+  if (alpha_split_const_mov (DImode, operands))
     DONE;
   else
     FAIL;
@@ -6103,6 +6101,19 @@
     DONE;
 })
 
+(define_split
+  [(set (match_operand:VEC 0 "register_operand" "")
+	(match_operand:VEC 1 "non_zero_const_operand" ""))]
+  ""
+  [(const_int 0)]
+{
+  if (alpha_split_const_mov (<MODE>mode, operands))
+    DONE;
+  else
+    FAIL;
+})
+
+
 (define_expand "movmisalign<mode>"
   [(set (match_operand:VEC 0 "nonimmediate_operand" "")
         (match_operand:VEC 1 "general_operand" ""))]
@@ -6113,13 +6124,14 @@
 })
 
 (define_insn "*mov<mode>_fix"
-  [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
-	(match_operand:VEC 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
+  [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
+	(match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
   "TARGET_FIX
    && (register_operand (operands[0], <MODE>mode)
        || reg_or_0_operand (operands[1], <MODE>mode))"
   "@
    bis $31,%r1,%0
+   #
    ldq %0,%1
    stq %r1,%0
    cpys %R1,%R1,%0
@@ -6127,22 +6139,23 @@
    stt %R1,%0
    ftoit %1,%0
    itoft %1,%0"
-  [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
+  [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
 
 (define_insn "*mov<mode>_nofix"
-  [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
-	(match_operand:VEC 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
+  [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
+	(match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
   "! TARGET_FIX
    && (register_operand (operands[0], <MODE>mode)
        || reg_or_0_operand (operands[1], <MODE>mode))"
   "@
    bis $31,%r1,%0
+   #
    ldq %0,%1
    stq %r1,%0
    cpys %R1,%R1,%0
    ldt %0,%1
    stt %R1,%0"
-  [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
+  [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
 
 (define_insn "uminv8qi3"
   [(set (match_operand:V8QI 0 "register_operand" "=r")

gcc/config/alpha/predicates.md

@@ -66,6 +66,17 @@
 		 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O')")
     (match_operand 0 "register_operand")))
 
+;; Return 1 if the operand is a non-symbolic constant operand that
+;; does not satisfy add_operand.
+(define_predicate "non_add_const_operand"
+  (and (match_code "const_int,const_double,const_vector")
+       (not (match_operand 0 "add_operand"))))
+
+;; Return 1 if the operand is a non-symbolic, non-zero constant operand.
+(define_predicate "non_zero_const_operand"
+  (and (match_code "const_int,const_double,const_vector")
+       (match_test "op != CONST0_RTX (mode)")))
+
 ;; Return 1 if OP is the constant 4 or 8.
 (define_predicate "const48_operand"
   (and (match_code "const_int")
@@ -205,11 +216,19 @@
 	      && general_operand (op, mode));
 
     case CONST_DOUBLE:
+      return op == CONST0_RTX (mode);
+
     case CONST_VECTOR:
+      if (reload_in_progress || reload_completed)
+	return alpha_legitimate_constant_p (op);
       return op == CONST0_RTX (mode);
 
     case CONST_INT:
-      return mode == QImode || mode == HImode || add_operand (op, mode);
+      if (mode == QImode || mode == HImode)
+	return true;
+      if (reload_in_progress || reload_completed)
+	return alpha_legitimate_constant_p (op);
+      return add_operand (op, mode);
 
     default:
       abort ();

gcc/testsuite/gcc.target/alpha/alpha.exp

+#   Copyright (C) 2005 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an Alpha target.
+if ![istarget alpha*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish

gcc/testsuite/gcc.target/alpha/pr19518.c

+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ev67" } */
+
+typedef short INT16;
+typedef unsigned int CARD32;
+typedef unsigned short CARD16;
+typedef unsigned char CARD8;
+typedef struct _Picture *PicturePtr;
+typedef int FbStride;
+typedef unsigned long __m64;
+extern __m64 load8888 (__m64);
+static __inline __m64 _mm_adds_pu8(__m64 __m1, __m64 __m2)
+{
+    return __m1 + __builtin_alpha_minsb8(__m2, ~__m1);
+}
+static __inline __m64 _mm_packs_pu16(__m64 __m1, __m64 __m2)
+{
+    __m1 = __builtin_alpha_minuw4(__m1, 0x00ff00ff00ff00ff);
+    __m2 = __builtin_alpha_minuw4(__m2, 0x00ff00ff00ff00ff);
+    return __m1 | (__m2 << 32);
+}
+typedef unsigned long long ullong;
+static __inline__ __m64 pix_multiply(__m64 a)
+{
+    if (a)
+	return a;
+}
+static __inline__ __m64 over(__m64 src, __m64 srca, __m64 dest)
+{
+    return _mm_adds_pu8(src, pix_multiply(dest));
+}
+
+void fbCompositeSolid_nx8888mmx(CARD8 op, PicturePtr pSrc, PicturePtr pMask,
+				INT16 yDst, CARD16 width, CARD16 height)
+{
+    CARD32 src;
+    CARD32 *dstLine, *dst;
+    CARD16 w;
+    FbStride dstStride;
+    __m64 vsrc, vsrca;
+    vsrc = load8888(src);
+    while (height--) {
+	dst = dstLine;
+	dstLine += dstStride;
+	while (w && (unsigned long) dst & 7) {
+	    *dst = _mm_packs_pu16(_mm_adds_pu8(vsrc, load8888(*dst)),
+				  _mm_setzero_si64());
+	    dst++;
+	}
+	while (w >= 2) {
+	    __m64 dest0, dest1;
+	    *(__m64 *) dst = _mm_packs_pu16(dest0, dest1);
+	    w -= 2;
+	}
+	while (w) {
+	    *dst = _mm_packs_pu16(_mm_adds_pu8(vsrc, pix_multiply(0)), 0);
+	    w--;
+	}
+    }
+}