Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
71cb39e6
Commit
71cb39e6
authored
Jun 15, 2005
by
Richard Sandiford
Committed by
Richard Sandiford
Jun 15, 2005
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
* doc/invoke.texi (-mips16): Fix typo.
From-SVN: r100981
parent
18ea791f
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
5 additions
and
1 deletions
+5
-1
gcc/ChangeLog
+4
-0
gcc/doc/invoke.texi
+1
-1
No files found.
gcc/ChangeLog
View file @
71cb39e6
2005-06-15 Richard Sandiford <richard@codesourcery.com>
* doc/invoke.texi (-mips16): Fix typo.
2005-06-15 David Ung <davidu@mips.com>
* config/mips/mips.h (GENERATE_MIPS16E): New definition.
...
...
gcc/doc/invoke.texi
View file @
71cb39e6
...
...
@@ -9862,7 +9862,7 @@ Equivalent to @samp{-march=mips64}.
@opindex mips16
@opindex mno-mips16
Generate (do not generate) MIPS16 code. If GCC is targetting a
MIP32 or MIPS64 architecture, it will make use of the MIPS16e ASE@.
MIP
S
32 or MIPS64 architecture, it will make use of the MIPS16e ASE@.
@item -mabi=32
@itemx -mabi=o64
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment