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riscv-gcc-1
Commit 719938ae by Uros Bizjak
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i386.md (extendsidi2 splitter): Also check for DX_REG when generating cltd insn. 

	* config/i386/i386.md (extendsidi2 splitter): Also check for DX_REG
	when generating cltd insn.

	(*ashl<mode>3_1): Remove special handling for register operand 2.
	(*ashlsi3_1_zext): Ditto.
	(*ashlhi3_1): Ditto.
	(*ashlhi3_1_lea): Ditto.
	(*ashlqi3_1): Ditto.
	(*ashlqi3_1_lea): Ditto.
	(*<shiftrt_insn><mode>3_1): Ditto.
	(*<shiftrt_insn>si3_1_zext): Ditto.
	(*<shiftrt_insn>qi3_1_slp): Ditto.
	(*<rotate_insn><mode>3_1): Ditto.
	(*<rotate_insn>si3_1_zext): Ditto.
	(*<rotate_insn>qi3_1_slp): Ditto.

From-SVN: r158261
parent 3e8542ca
Showing with 55 additions and 69 deletions
gcc/ChangeLog
2010-04-13 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (extendsidi2 splitter): Also check for DX_REG
when generating cltd insn.
(*ashl<mode>3_1): Remove special handling for register operand 2.
(*ashlsi3_1_zext): Ditto.
(*ashlhi3_1): Ditto.
(*ashlhi3_1_lea): Ditto.
(*ashlqi3_1): Ditto.
(*ashlqi3_1_lea): Ditto.
(*<shiftrt_insn><mode>3_1): Ditto.
(*<shiftrt_insn>si3_1_zext): Ditto.
(*<shiftrt_insn>qi3_1_slp): Ditto.
(*<rotate_insn><mode>3_1): Ditto.
(*<rotate_insn>si3_1_zext): Ditto.
(*<rotate_insn>qi3_1_slp): Ditto.
2010-04-13 Richard Guenther <rguenther@suse.de>
* tree-ssa-structalias.c (callused_id): Remove.
......@@ -126,8 +144,7 @@
plugin name.
(default_plugin_dir_name): Added new function.
* common.opt (iplugindir): New option to set the plugin
directory.
* common.opt (iplugindir): New option to set the plugin directory.
2010-04-12 Uros Bizjak <ubizjak@gmail.com>
......
gcc/config/i386/i386.md
......@@ -4228,7 +4228,8 @@
/* Generate a cltd if possible and doing so it profitable. */
if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
&& true_regnum (operands[3]) == AX_REG)
&& true_regnum (operands[3]) == AX_REG
&& true_regnum (operands[4]) == DX_REG)
{
emit_insn (gen_ashrsi3_cvt (operands[4], operands[3], GEN_INT (31)));
DONE;
......@@ -9702,19 +9703,17 @@
{
switch (get_attr_type (insn))
{
case TYPE_LEA:
return "#";
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "add{<imodesuffix>}\t%0, %0";
case TYPE_LEA:
return "#";
default:
if (REG_P (operands[2]))
return "sal{<imodesuffix>}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{<imodesuffix>}\t%0";
else
return "sal{<imodesuffix>}\t{%2, %0|%0, %2}";
......@@ -9751,18 +9750,16 @@
{
switch (get_attr_type (insn))
{
case TYPE_LEA:
return "#";
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
return "add{l}\t%k0, %k0";
case TYPE_LEA:
return "#";
default:
if (REG_P (operands[2]))
return "sal{l}\t{%b2, %k0|%k0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{l}\t%k0";
else
return "sal{l}\t{%2, %k0|%k0, %2}";
......@@ -9803,10 +9800,8 @@
return "add{w}\t%0, %0";
default:
if (REG_P (operands[2]))
return "sal{w}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
......@@ -9843,15 +9838,14 @@
{
case TYPE_LEA:
return "#";
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
return "add{w}\t%0, %0";
default:
if (REG_P (operands[2]))
return "sal{w}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
......@@ -9896,18 +9890,11 @@
return "add{b}\t%0, %0";
default:
if (REG_P (operands[2]))
{
if (get_attr_mode (insn) == MODE_SI)
return "sal{l}\t{%b2, %k0|%k0, %b2}";
else
return "sal{b}\t{%b2, %0|%0, %b2}";
}
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
{
if (get_attr_mode (insn) == MODE_SI)
return "sal{l}\t%0";
return "sal{l}\t%k0";
else
return "sal{b}\t%0";
}
......@@ -9952,6 +9939,7 @@
{
case TYPE_LEA:
return "#";
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
......@@ -9960,18 +9948,11 @@
return "add{b}\t%0, %0";
default:
if (REG_P (operands[2]))
{
if (get_attr_mode (insn) == MODE_SI)
return "sal{l}\t{%b2, %k0|%k0, %b2}";
else
return "sal{b}\t{%b2, %0|%0, %b2}";
}
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
{
if (get_attr_mode (insn) == MODE_SI)
return "sal{l}\t%0";
return "sal{l}\t%k0";
else
return "sal{b}\t%0";
}
......@@ -10384,10 +10365,8 @@
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
if (REG_P (operands[2]))
return "<shiftrt>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<shiftrt>{<imodesuffix>}\t%0";
else
return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
......@@ -10410,10 +10389,8 @@
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
{
if (REG_P (operands[2]))
return "<shiftrt>{l}\t{%b2, %k0|%k0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<shiftrt>{l}\t%k0";
else
return "<shiftrt>{l}\t{%2, %k0|%k0, %2}";
......@@ -10438,10 +10415,8 @@
|| (operands[1] == const1_rtx
&& TARGET_SHIFT1))"
{
if (REG_P (operands[1]))
return "<shiftrt>{b}\t{%b1, %0|%0, %b1}";
else if (operands[1] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[1] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<shiftrt>{b}\t%0";
else
return "<shiftrt>{b}\t{%1, %0|%0, %1}";
......@@ -10661,10 +10636,8 @@
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
if (REG_P (operands[2]))
return "<rotate>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<rotate>{<imodesuffix>}\t%0";
else
return "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
......@@ -10687,10 +10660,8 @@
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
{
if (REG_P (operands[2]))
return "<rotate>{l}\t{%b2, %k0|%k0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<rotate>{l}\t%k0";
else
return "<rotate>{l}\t{%2, %k0|%k0, %2}";
......@@ -10715,10 +10686,8 @@
|| (operands[1] == const1_rtx
&& TARGET_SHIFT1))"
{
if (REG_P (operands[1]))
return "<rotate>{b}\t{%b1, %0|%0, %b1}";
else if (operands[1] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
if (operands[1] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<rotate>{b}\t%0";
else
return "<rotate>{b}\t{%1, %0|%0, %1}";
......
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