Commit 716b5162 by Michael Meissner

Undo previous change to REG_ALLOC_ORDER.

From-SVN: r7963
parent b8592c8e
...@@ -259,15 +259,15 @@ extern int target_flags; ...@@ -259,15 +259,15 @@ extern int target_flags;
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
{ 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } { 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
/* Order in which to allocate registers. Each register must be /* Order in which to allocate registers. First allocate registers
listed once, even those in FIXED_REGISTERS. List frame pointer for which no insn operand demands that register, next those that are
late and fixed registers last. Note that, in general, we prefer demanded by the least number of insns. List frame pointer late and fixed
registers listed in CALL_USED_REGISTERS, keeping the others egisters last. Note that, in general, we want to put nonsaved registers
available for storage of persistent values. */ late, but we put bx relatively early since it is not demanded by
any insn operand. */
#define REG_ALLOC_ORDER \ #define REG_ALLOC_ORDER \
/*ax,cx,dx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ /*si,di,bx,cx,dx,ax,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
{ 0, 2, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 } { 4, 5, 3, 2, 1, 0, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
/* Macro to conditionally modify fixed_regs/call_used_regs. */ /* Macro to conditionally modify fixed_regs/call_used_regs. */
#define CONDITIONAL_REGISTER_USAGE \ #define CONDITIONAL_REGISTER_USAGE \
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment