Commit 713877cb by Claudiu Zissulescu Committed by Claudiu Zissulescu

[ARC] Fix ARC target specific tests.

Fix ARC specific tests by improving the matching pattern and adding
the missing functionality in arc.exp

gcc/tests
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/add_n-combine.c: Match add1/2/3 instruction in
	output assembly.
	* gcc.target/arc/arc.exp (check_effective_target_codedensity):
	Add.
	* gcc.target/arc/cmem-7.c: Fix matching patterns.
	* gcc.target/arc/cmem-bit-1.c: Likewise.
	* gcc.target/arc/cmem-bit-2.c: Likewise.
	* gcc.target/arc/cmem-bit-3.c: Likewise.
	* gcc.target/arc/cmem-bit-4.c: Likewise.
	* gcc.target/arc/interrupt-2.c: Match rtie insn for A7.
	* gcc.target/arc/store-merge-1.c: This test is only meaningful for
	architectures with double load/store operations.

From-SVN: r278609
parent 7028c217
2019-11-22 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/add_n-combine.c: Match add1/2/3 instruction in
output assembly.
* gcc.target/arc/arc.exp (check_effective_target_codedensity):
Add.
* gcc.target/arc/cmem-7.c: Fix matching patterns.
* gcc.target/arc/cmem-bit-1.c: Likewise.
* gcc.target/arc/cmem-bit-2.c: Likewise.
* gcc.target/arc/cmem-bit-3.c: Likewise.
* gcc.target/arc/cmem-bit-4.c: Likewise.
* gcc.target/arc/interrupt-2.c: Match rtie insn for A7.
* gcc.target/arc/store-merge-1.c: This test is only meaningful for
architectures with double load/store operations.
2019-11-21 Martin Sebor <msebor@redhat.com> 2019-11-21 Martin Sebor <msebor@redhat.com>
* gcc.dg/strlenopt-66.c: Avoid buffer overflow. Add more test cases. * gcc.dg/strlenopt-66.c: Avoid buffer overflow. Add more test cases.
......
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-options "-O2 -fdump-rtl-combine" } */ /* { dg-options "-O2" } */
struct b1 { struct b1 {
char c; char c;
...@@ -45,4 +45,6 @@ void f() { ...@@ -45,4 +45,6 @@ void f() {
a(at3.bn[bu]); a(at3.bn[bu]);
} }
/* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */ /* { dg-final { scan-assembler "add1" } } */
/* { dg-final { scan-assembler "add2" } } */
/* { dg-final { scan-assembler "add3" } } */
...@@ -94,6 +94,16 @@ proc check_effective_target_barrelshifter { } { ...@@ -94,6 +94,16 @@ proc check_effective_target_barrelshifter { } {
}] }]
} }
#return 1 if we have code density option on.
proc check_effective_target_codedensity { } {
return [check_no_compiler_messages codedensity assembly {
#if !defined(__ARC_CODE_DENSITY__)
#error No code density option for this config
#endif
}]
}
#return 1 if we use ARCv2 Accumulator registers #return 1 if we use ARCv2 Accumulator registers
proc check_effective_target_accregs { } { proc check_effective_target_accregs { } {
return [check_no_compiler_messages accregs assembly { return [check_no_compiler_messages accregs assembly {
......
...@@ -21,7 +21,7 @@ some_function () ...@@ -21,7 +21,7 @@ some_function ()
return 0; return 0;
} }
/* { dg-final { scan-assembler "xldb \[^\n\]*@ss" } } */ /* { dg-final { scan-assembler "xldb\\s+\[^\n\]*@ss" } } */
/* { dg-final { scan-assembler "xstb \[^\n\]*@ss" } } */ /* { dg-final { scan-assembler "xstb\\s+\[^\n\]*@ss" } } */
/* { dg-final { scan-assembler-not "xldb \[^\n\]*@tt" } } */ /* { dg-final { scan-assembler-not "xldb\\s+\[^\n\]*@tt" } } */
/* { dg-final { scan-assembler-not "xstb \[^\n\]*@tt" } } */ /* { dg-final { scan-assembler-not "xstb\\s+\[^\n\]*@tt" } } */
...@@ -16,5 +16,5 @@ void foo() { ...@@ -16,5 +16,5 @@ void foo() {
bar(); bar();
} }
/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */ /* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } } */ /* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* } } } */
...@@ -16,5 +16,5 @@ void foo() { ...@@ -16,5 +16,5 @@ void foo() {
bar(); bar();
} }
/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */ /* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } } */ /* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* } } } */
...@@ -16,5 +16,5 @@ void foo() { ...@@ -16,5 +16,5 @@ void foo() {
bar(); bar();
} }
/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */ /* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } } */ /* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* } } } */
...@@ -16,5 +16,5 @@ void foo() { ...@@ -16,5 +16,5 @@ void foo() {
bar(); bar();
} }
/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */ /* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } } */ /* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* } } } */
...@@ -3,4 +3,5 @@ void __attribute__ ((interrupt("ilink2"))) ...@@ -3,4 +3,5 @@ void __attribute__ ((interrupt("ilink2")))
handler1 (void) handler1 (void)
{ {
} }
/* { dg-final { scan-assembler-times "j.*\[ilink2\]" 1 } } */ /* { dg-final { scan-assembler-times "j.*\[ilink2\]" 1 { target { arc6xx } } } } */
/* { dg-final { scan-assembler-times "rtie" 1 { target { arc700 } } } } */
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-options "-O3" } */ /* { dg-require-effective-target archs }*/
/* { dg-options "-O3 -mll64" } */
/* This tests checks if we use st w6,[reg] format. */ /* This tests checks if we use st w6,[reg] format. */
......
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