mips.md (extended_mips16): Include GOT and constant-pool loads.

gcc/
	* config/mips/mips.md (extended_mips16): Include GOT and constant-pool
	loads.
	(insn_count): New attribute, with most cases extracted from...
	(length): ...here.  Redefine most cases in terms of insn_count.
	(single_insn): Delete.
	(can_delay): Use insn_count to check for single instructions.
	(*mul<mode>3_r4300, mul<mode>3_r4000, *mul_acc_si, *mul_acc_si_r3900)
	(*msac_using_macc, *mul_sub_si, <u>mulsidi3_32bit_r4000)
	(<u>mulsidi3_64bit_r4000, <su>muldi3_highpart_internal)
	(<su>mulsi3_highpart_split, <su>muldi3_highpart_internal)
	(<u>mulditi3_r4000, *div<mode>3, *recip<mode>3, divmod<mode>4)
	(udivmod<mode>4, sqrt<mode>2, *rsqrt<mode>a, *rsqrt<mode>b)
	(fix_truncdfsi2_macro, fix_truncsfsi2_macro, *lea_high64)
	(*lea64, cprestore_<mode>, clear_hazard_<mode>, <unnamed insn>)
	(casesi_internal_mips16_<mode>, *tls_get_tp_<mode>_split)
	(tls_get_tp_mips16, *tls_get_tp_mips16_call_<mode>): Use "insn_count"
	rather than "length".
	(tls_get_tp_<mode>): Likewise.  Remove redundant "no_delay" attribute.
	* config/mips/mips-ps-3d.md (mips_c_cond_4s, mips_cabs_cond_4s):
	Use "insn_count" rather than "length".
	* config/mips/mips-dsp.md
	(mips_l<SHORT:size><u>x_ext<GPR:mode>_<P:mode>)
	(mips_l<GPR:size>x_<P:mode>, *mips_lw<u>x_<P:mode>_ext): Remove
	length attributes.

gcc/testsuite/
	* gcc.target/mips/umips-branch-1.c, gcc.target/mips/umips-branch-2.c:
	New tests.

From-SVN: r200037

gcc/ChangeLog

+2013-06-12  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* config/mips/mips.md (extended_mips16): Include GOT and constant-pool
+	loads.
+	(insn_count): New attribute, with most cases extracted from...
+	(length): ...here.  Redefine most cases in terms of insn_count.
+	(single_insn): Delete.
+	(can_delay): Use insn_count to check for single instructions.
+	(*mul<mode>3_r4300, mul<mode>3_r4000, *mul_acc_si, *mul_acc_si_r3900)
+	(*msac_using_macc, *mul_sub_si, <u>mulsidi3_32bit_r4000)
+	(<u>mulsidi3_64bit_r4000, <su>muldi3_highpart_internal)
+	(<su>mulsi3_highpart_split, <su>muldi3_highpart_internal)
+	(<u>mulditi3_r4000, *div<mode>3, *recip<mode>3, divmod<mode>4)
+	(udivmod<mode>4, sqrt<mode>2, *rsqrt<mode>a, *rsqrt<mode>b)
+	(fix_truncdfsi2_macro, fix_truncsfsi2_macro, *lea_high64)
+	(*lea64, cprestore_<mode>, clear_hazard_<mode>, <unnamed insn>)
+	(casesi_internal_mips16_<mode>, *tls_get_tp_<mode>_split)
+	(tls_get_tp_mips16, *tls_get_tp_mips16_call_<mode>): Use "insn_count"
+	rather than "length".
+	(tls_get_tp_<mode>): Likewise.  Remove redundant "no_delay" attribute.
+	* config/mips/mips-ps-3d.md (mips_c_cond_4s, mips_cabs_cond_4s):
+	Use "insn_count" rather than "length".
+	* config/mips/mips-dsp.md
+	(mips_l<SHORT:size><u>x_ext<GPR:mode>_<P:mode>)
+	(mips_l<GPR:size>x_<P:mode>, *mips_lw<u>x_<P:mode>_ext): Remove
+	length attributes.
+
 2013-06-12  Marc Glisse  <marc.glisse@inria.fr>
 
 	PR tree-optimization/57361

gcc/config/mips/mips-dsp.md

@@ -1131,8 +1131,7 @@
   "ISA_HAS_L<SHORT:SIZE><U>X"
   "l<SHORT:size><u>x\t%0,%2(%1)"
   [(set_attr "type"	"load")
-   (set_attr "mode"	"<GPR:MODE>")
-   (set_attr "length"	"4")])
+   (set_attr "mode"	"<GPR:MODE>")])
 
 (define_expand "mips_lhx"
   [(match_operand:SI 0 "register_operand")
@@ -1165,8 +1164,7 @@
   "ISA_HAS_L<GPR:SIZE>X"
   "l<GPR:size>x\t%0,%2(%1)"
   [(set_attr "type"	"load")
-   (set_attr "mode"	"<GPR:MODE>")
-   (set_attr "length"	"4")])
+   (set_attr "mode"	"<GPR:MODE>")])
 
 (define_insn "*mips_lw<u>x_<P:mode>_ext"
   [(set (match_operand:DI 0 "register_operand" "=d")
@@ -1176,8 +1174,7 @@
   "ISA_HAS_LW<U>X && TARGET_64BIT"
   "lw<u>x\t%0,%2(%1)"
   [(set_attr "type"	"load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
+   (set_attr "mode"	"DI")])
 
 ;; Table 2-8. MIPS DSP ASE Instructions: Branch
 ;; BPOSGE32

gcc/config/mips/mips-ps-3d.md

@@ -481,7 +481,7 @@
   operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
 }
   [(set_attr "type" "fcmp")
-   (set_attr "length" "8")
+   (set_attr "insn_count" "2")
    (set_attr "mode" "FPSW")])
 
 (define_insn_and_split "mips_cabs_cond_4s"
@@ -510,7 +510,7 @@
   operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
 }
   [(set_attr "type" "fcmp")
-   (set_attr "length" "8")
+   (set_attr "insn_count" "2")
    (set_attr "mode" "FPSW")])
 
 

gcc/testsuite/ChangeLog

+2013-06-12  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* gcc.target/mips/umips-branch-1.c, gcc.target/mips/umips-branch-2.c:
+	New tests.
+
 2013-06-12  Marc Glisse  <marc.glisse@inria.fr>
 
 	PR tree-optimization/57361

gcc/testsuite/gcc.target/mips/umips-branch-1.c

+/* { dg-options "(-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+int MICROMIPS
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tmove\t\\\$2,\\\$0" } } */

gcc/testsuite/gcc.target/mips/umips-branch-2.c

+/* { dg-options "(-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+int MICROMIPS
+foo (int *x)
+{
+  return x[5000];
+}
+
+/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tlw\t\\\$2,20000\\(\\\$4\\)" } } */