Skip to content

R
riscv-gcc-1
Commit 70ee78ec by Richard Kenner
Options

(divsi3, modsi3, udivsi3): Comment out. 

(extendsfsd2_no_tp): Add alternative with output in MEM, input in REG.

From-SVN: r14373
parent 844dadc7
Showing with 70 additions and 65 deletions
gcc/config/alpha/alpha.md
...@@ -623,57 +623,61 @@ ...@@ -623,57 +623,61 @@
;; The divide and remainder operations always take their inputs from ;; The divide and remainder operations always take their inputs from
;; r24 and r25, put their output in r27, and clobber r23 and r28. ;; r24 and r25, put their output in r27, and clobber r23 and r28.
(define_expand "divsi3" ;; ??? comment out the divsi routines since the library functions
[(set (reg:SI 24) (match_operand:SI 1 "input_operand" "")) ;; don't seem to do the right thing with the high 32-bits of a
(set (reg:SI 25) (match_operand:SI 2 "input_operand" "")) ;; register nonzero.
(parallel [(set (reg:SI 27)
(div:SI (reg:SI 24) ;(define_expand "divsi3"
(reg:SI 25))) ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
(clobber (reg:DI 23)) ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
(clobber (reg:DI 28))]) ; (parallel [(set (reg:SI 27)
(set (match_operand:SI 0 "general_operand" "") ; (div:SI (reg:SI 24)
(reg:SI 27))] ; (reg:SI 25)))
"!TARGET_OPEN_VMS" ; (clobber (reg:DI 23))
"") ; (clobber (reg:DI 28))])
; (set (match_operand:SI 0 "general_operand" "")
(define_expand "udivsi3" ; (reg:SI 27))]
[(set (reg:SI 24) (match_operand:SI 1 "input_operand" "")) ; "!TARGET_OPEN_VMS"
(set (reg:SI 25) (match_operand:SI 2 "input_operand" "")) ; "")
(parallel [(set (reg:SI 27)
(udiv:SI (reg:SI 24) ;(define_expand "udivsi3"
(reg:SI 25))) ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
(clobber (reg:DI 23)) ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
(clobber (reg:DI 28))]) ; (parallel [(set (reg:SI 27)
(set (match_operand:SI 0 "general_operand" "") ; (udiv:SI (reg:SI 24)
(reg:SI 27))] ; (reg:SI 25)))
"!TARGET_OPEN_VMS" ; (clobber (reg:DI 23))
"") ; (clobber (reg:DI 28))])
; (set (match_operand:SI 0 "general_operand" "")
(define_expand "modsi3" ; (reg:SI 27))]
[(set (reg:SI 24) (match_operand:SI 1 "input_operand" "")) ; "!TARGET_OPEN_VMS"
(set (reg:SI 25) (match_operand:SI 2 "input_operand" "")) ; "")
(parallel [(set (reg:SI 27)
(mod:SI (reg:SI 24) ;(define_expand "modsi3"
(reg:SI 25))) ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
(clobber (reg:DI 23)) ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
(clobber (reg:DI 28))]) ; (parallel [(set (reg:SI 27)
(set (match_operand:SI 0 "general_operand" "") ; (mod:SI (reg:SI 24)
(reg:SI 27))] ; (reg:SI 25)))
"!TARGET_OPEN_VMS" ; (clobber (reg:DI 23))
"") ; (clobber (reg:DI 28))])
; (set (match_operand:SI 0 "general_operand" "")
(define_expand "umodsi3" ; (reg:SI 27))]
[(set (reg:SI 24) (match_operand:SI 1 "input_operand" "")) ; "!TARGET_OPEN_VMS"
(set (reg:SI 25) (match_operand:SI 2 "input_operand" "")) ; "")
(parallel [(set (reg:SI 27)
(umod:SI (reg:SI 24) ;(define_expand "umodsi3"
(reg:SI 25))) ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
(clobber (reg:DI 23)) ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
(clobber (reg:DI 28))]) ; (parallel [(set (reg:SI 27)
(set (match_operand:SI 0 "general_operand" "") ; (umod:SI (reg:SI 24)
(reg:SI 27))] ; (reg:SI 25)))
"!TARGET_OPEN_VMS" ; (clobber (reg:DI 23))
"") ; (clobber (reg:DI 28))])
; (set (match_operand:SI 0 "general_operand" "")
; (reg:SI 27))]
; "!TARGET_OPEN_VMS"
; "")
(define_expand "divdi3" (define_expand "divdi3"
[(set (reg:DI 24) (match_operand:DI 1 "input_operand" "")) [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
...@@ -727,15 +731,15 @@ ...@@ -727,15 +731,15 @@
"!TARGET_OPEN_VMS" "!TARGET_OPEN_VMS"
"") "")
(define_insn "" ;(define_insn ""
[(set (reg:SI 27) ; [(set (reg:SI 27)
(match_operator:SI 1 "divmod_operator" ; (match_operator:SI 1 "divmod_operator"
[(reg:SI 24) (reg:SI 25)])) ; [(reg:SI 24) (reg:SI 25)]))
(clobber (reg:DI 23)) ; (clobber (reg:DI 23))
(clobber (reg:DI 28))] ; (clobber (reg:DI 28))]
"!TARGET_OPEN_VMS" ; "!TARGET_OPEN_VMS"
"%E1 $24,$25,$27" ; "%E1 $24,$25,$27"
[(set_attr "type" "isubr")]) ; [(set_attr "type" "isubr")])
(define_insn "" (define_insn ""
[(set (reg:DI 27) [(set (reg:DI 27)
...@@ -1509,13 +1513,14 @@ ...@@ -1509,13 +1513,14 @@
(set_attr "trap" "yes")]) (set_attr "trap" "yes")])
(define_insn "extendsfdf2_no_tp" (define_insn "extendsfdf2_no_tp"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f,m")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))] (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
"TARGET_FP && alpha_tp != ALPHA_TP_INSN" "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
"@ "@
add%-%)%& $f31,%1,%0 cpys %1,%1,%0
ld%, %0,%1" ld%, %0,%1
[(set_attr "type" "fadd,ld") st%- %1,%0"
[(set_attr "type" "fcpys,ld,st")
(set_attr "trap" "yes")]) (set_attr "trap" "yes")])
(define_insn "" (define_insn ""
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment