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Commit 70d22cdd by Jakub Jelinek Committed by Jakub Jelinek
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re PR target/85918 (Conversions to/from [unsigned] long long are not vectorized… 

re PR target/85918 (Conversions to/from [unsigned] long long are not vectorized for AVX512DQ target)

	PR target/85918
	* config/i386/i386.md (fixunssuffix, floatunssuffix): New code
	attributes.
	* config/i386/sse.md
	(<floatsuffix>float<sseintvecmodelower><mode>2<mask_name><round_name>):
	Rename to ...
	(float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>):
	... this.
	(<floatsuffix>float<sselongvecmodelower><mode>2<mask_name><round_name>):
	Rename to ...
	(float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>):
	... this.
	(*<floatsuffix>floatv2div2sf2): Rename to ...
	(*float<floatunssuffix>v2div2sf2): ... this.
	(<floatsuffix>floatv2div2sf2_mask): Rename to ...
	(float<floatunssuffix>v2div2sf2_mask): ... this.
	(*<floatsuffix>floatv2div2sf2_mask_1): Rename to ...
	(*float<floatunssuffix>v2div2sf2_mask_1): ... this.
	(<fixsuffix>fix_truncv8dfv8si2<mask_name><round_saeonly_name>): Rename
	to ...
	(fix<fixunssuffix>_truncv8dfv8si2<mask_name><round_saeonly_name>):
	... this.
	(<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>):
	Rename to ...
	(fix<fixunssuffix>_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>):
	... this.
	(<fixsuffix>fix_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
	Rename to ...
	(fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
	... this.
	(<fixsuffix>fix_truncv2sfv2di2<mask_name>): Rename to ...
	(fix<fixunssuffix>_truncv2sfv2di2<mask_name>): ... this.
	(vec_pack_ufix_trunc_<mode>): Use gen_fixuns_truncv8dfv8si2 instead of
	gen_ufix_truncv8dfv8si2.
	* config/i386/i386-builtin.def (__builtin_ia32_cvttpd2uqq256_mask,
	__builtin_ia32_cvttpd2uqq128_mask, __builtin_ia32_cvttps2uqq256_mask,
	__builtin_ia32_cvttps2uqq128_mask, __builtin_ia32_cvtuqq2ps256_mask,
	__builtin_ia32_cvtuqq2ps128_mask, __builtin_ia32_cvtuqq2pd256_mask,
	__builtin_ia32_cvtuqq2pd128_mask, __builtin_ia32_cvttpd2udq512_mask,
	__builtin_ia32_cvtuqq2ps512_mask, __builtin_ia32_cvtuqq2pd512_mask,
	__builtin_ia32_cvttps2uqq512_mask, __builtin_ia32_cvttpd2uqq512_mask):
	Use fixuns instead ufix or floatuns instead ufloat in CODE_FOR_ names.

	* gcc.target/i386/avx512dq-pr85918.c: New test.

From-SVN: r260797
parent 80c820d8
Showing with 106 additions and 12 deletions
gcc/ChangeLog
2018-05-27 Jakub Jelinek <jakub@redhat.com>
PR target/85918
* config/i386/i386.md (fixunssuffix, floatunssuffix): New code
attributes.
* config/i386/sse.md
(<floatsuffix>float<sseintvecmodelower><mode>2<mask_name><round_name>):
Rename to ...
(float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>):
... this.
(<floatsuffix>float<sselongvecmodelower><mode>2<mask_name><round_name>):
Rename to ...
(float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>):
... this.
(*<floatsuffix>floatv2div2sf2): Rename to ...
(*float<floatunssuffix>v2div2sf2): ... this.
(<floatsuffix>floatv2div2sf2_mask): Rename to ...
(float<floatunssuffix>v2div2sf2_mask): ... this.
(*<floatsuffix>floatv2div2sf2_mask_1): Rename to ...
(*float<floatunssuffix>v2div2sf2_mask_1): ... this.
(<fixsuffix>fix_truncv8dfv8si2<mask_name><round_saeonly_name>): Rename
to ...
(fix<fixunssuffix>_truncv8dfv8si2<mask_name><round_saeonly_name>):
... this.
(<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>):
Rename to ...
(fix<fixunssuffix>_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>):
... this.
(<fixsuffix>fix_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
Rename to ...
(fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
... this.
(<fixsuffix>fix_truncv2sfv2di2<mask_name>): Rename to ...
(fix<fixunssuffix>_truncv2sfv2di2<mask_name>): ... this.
(vec_pack_ufix_trunc_<mode>): Use gen_fixuns_truncv8dfv8si2 instead of
gen_ufix_truncv8dfv8si2.
* config/i386/i386-builtin.def (__builtin_ia32_cvttpd2uqq256_mask,
__builtin_ia32_cvttpd2uqq128_mask, __builtin_ia32_cvttps2uqq256_mask,
__builtin_ia32_cvttps2uqq128_mask, __builtin_ia32_cvtuqq2ps256_mask,
__builtin_ia32_cvtuqq2ps128_mask, __builtin_ia32_cvtuqq2pd256_mask,
__builtin_ia32_cvtuqq2pd128_mask, __builtin_ia32_cvttpd2udq512_mask,
__builtin_ia32_cvtuqq2ps512_mask, __builtin_ia32_cvtuqq2pd512_mask,
__builtin_ia32_cvttps2uqq512_mask, __builtin_ia32_cvttpd2uqq512_mask):
Use fixuns instead ufix or floatuns instead ufloat in CODE_FOR_ names.
2018-05-24 H.J. Lu <hongjiu.lu@intel.com> 2018-05-24 H.J. Lu <hongjiu.lu@intel.com>
PR target/85900 PR target/85900
......
gcc/config/i386/i386.md
...@@ -981,10 +981,12 @@ ...@@ -981,10 +981,12 @@
;; Used in signed and unsigned fix. ;; Used in signed and unsigned fix.
(define_code_iterator any_fix [fix unsigned_fix]) (define_code_iterator any_fix [fix unsigned_fix])
(define_code_attr fixsuffix [(fix "") (unsigned_fix "u")]) (define_code_attr fixsuffix [(fix "") (unsigned_fix "u")])
(define_code_attr fixunssuffix [(fix "") (unsigned_fix "uns")])
;; Used in signed and unsigned float. ;; Used in signed and unsigned float.
(define_code_iterator any_float [float unsigned_float]) (define_code_iterator any_float [float unsigned_float])
(define_code_attr floatsuffix [(float "") (unsigned_float "u")]) (define_code_attr floatsuffix [(float "") (unsigned_float "u")])
(define_code_attr floatunssuffix [(float "") (unsigned_float "uns")])
;; All integer modes. ;; All integer modes.
(define_mode_iterator SWI1248x [QI HI SI DI]) (define_mode_iterator SWI1248x [QI HI SI DI])
......
gcc/config/i386/sse.md
...@@ -4853,7 +4853,7 @@ ...@@ -4853,7 +4853,7 @@
(set_attr "prefix" "maybe_vex") (set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_insn "<floatsuffix>float<sseintvecmodelower><mode>2<mask_name><round_name>" (define_insn "float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>"
[(set (match_operand:VF2_AVX512VL 0 "register_operand" "=v") [(set (match_operand:VF2_AVX512VL 0 "register_operand" "=v")
(any_float:VF2_AVX512VL (any_float:VF2_AVX512VL
(match_operand:<sseintvecmode> 1 "nonimmediate_operand" "<round_constraint>")))] (match_operand:<sseintvecmode> 1 "nonimmediate_operand" "<round_constraint>")))]
...@@ -4863,7 +4863,7 @@ ...@@ -4863,7 +4863,7 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
;; For <floatsuffix>float<sselondveclower><mode> insn patterns ;; For float<floatunssuffix><sselondveclower><mode> insn patterns
(define_mode_attr qq2pssuff (define_mode_attr qq2pssuff
[(V8SF "") (V4SF "{y}")]) [(V8SF "") (V4SF "{y}")])
...@@ -4877,7 +4877,7 @@ ...@@ -4877,7 +4877,7 @@
[(V8SF "XI") (V4SF "OI") [(V8SF "XI") (V4SF "OI")
(V8DF "OI") (V4DF "TI")]) (V8DF "OI") (V4DF "TI")])
(define_insn "<floatsuffix>float<sselongvecmodelower><mode>2<mask_name><round_name>" (define_insn "float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>"
[(set (match_operand:VF1_128_256VL 0 "register_operand" "=v") [(set (match_operand:VF1_128_256VL 0 "register_operand" "=v")
(any_float:VF1_128_256VL (any_float:VF1_128_256VL
(match_operand:<sselongvecmode> 1 "nonimmediate_operand" "<round_constraint>")))] (match_operand:<sselongvecmode> 1 "nonimmediate_operand" "<round_constraint>")))]
...@@ -4887,7 +4887,7 @@ ...@@ -4887,7 +4887,7 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_insn "*<floatsuffix>floatv2div2sf2" (define_insn "*float<floatunssuffix>v2div2sf2"
[(set (match_operand:V4SF 0 "register_operand" "=v") [(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_concat:V4SF (vec_concat:V4SF
(any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm")) (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm"))
...@@ -4898,7 +4898,7 @@ ...@@ -4898,7 +4898,7 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
(define_insn "<floatsuffix>floatv2div2sf2_mask" (define_insn "float<floatunssuffix>v2div2sf2_mask"
[(set (match_operand:V4SF 0 "register_operand" "=v") [(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_concat:V4SF (vec_concat:V4SF
(vec_merge:V2SF (vec_merge:V2SF
...@@ -4914,7 +4914,7 @@ ...@@ -4914,7 +4914,7 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
(define_insn "*<floatsuffix>floatv2div2sf2_mask_1" (define_insn "*float<floatunssuffix>v2div2sf2_mask_1"
[(set (match_operand:V4SF 0 "register_operand" "=v") [(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_concat:V4SF (vec_concat:V4SF
(vec_merge:V2SF (vec_merge:V2SF
...@@ -5084,7 +5084,7 @@ ...@@ -5084,7 +5084,7 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "<fixsuffix>fix_truncv8dfv8si2<mask_name><round_saeonly_name>" (define_insn "fix<fixunssuffix>_truncv8dfv8si2<mask_name><round_saeonly_name>"
[(set (match_operand:V8SI 0 "register_operand" "=v") [(set (match_operand:V8SI 0 "register_operand" "=v")
(any_fix:V8SI (any_fix:V8SI
(match_operand:V8DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))] (match_operand:V8DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
...@@ -5123,7 +5123,7 @@ ...@@ -5123,7 +5123,7 @@
(set_attr "prefix" "maybe_evex") (set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")]) (set_attr "mode" "OI")])
(define_insn "<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>" (define_insn "fix<fixunssuffix>_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>"
[(set (match_operand:<sseintvecmode> 0 "register_operand" "=v") [(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
(any_fix:<sseintvecmode> (any_fix:<sseintvecmode>
(match_operand:VF2_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))] (match_operand:VF2_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
...@@ -5155,7 +5155,7 @@ ...@@ -5155,7 +5155,7 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "<sseintvecmode2>")]) (set_attr "mode" "<sseintvecmode2>")])
(define_insn "<fixsuffix>fix_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>" (define_insn "fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>"
[(set (match_operand:<sselongvecmode> 0 "register_operand" "=v") [(set (match_operand:<sselongvecmode> 0 "register_operand" "=v")
(any_fix:<sselongvecmode> (any_fix:<sselongvecmode>
(match_operand:VF1_128_256VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))] (match_operand:VF1_128_256VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
...@@ -5165,7 +5165,7 @@ ...@@ -5165,7 +5165,7 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "<sseintvecmode3>")]) (set_attr "mode" "<sseintvecmode3>")])
(define_insn "<fixsuffix>fix_truncv2sfv2di2<mask_name>" (define_insn "fix<fixunssuffix>_truncv2sfv2di2<mask_name>"
[(set (match_operand:V2DI 0 "register_operand" "=v") [(set (match_operand:V2DI 0 "register_operand" "=v")
(any_fix:V2DI (any_fix:V2DI
(vec_select:V2SF (vec_select:V2SF
...@@ -5961,8 +5961,8 @@ ...@@ -5961,8 +5961,8 @@
r1 = gen_reg_rtx (V8SImode); r1 = gen_reg_rtx (V8SImode);
r2 = gen_reg_rtx (V8SImode); r2 = gen_reg_rtx (V8SImode);
emit_insn (gen_ufix_truncv8dfv8si2 (r1, operands[1])); emit_insn (gen_fixuns_truncv8dfv8si2 (r1, operands[1]));
emit_insn (gen_ufix_truncv8dfv8si2 (r2, operands[2])); emit_insn (gen_fixuns_truncv8dfv8si2 (r2, operands[2]));
emit_insn (gen_avx_vec_concatv16si (operands[0], r1, r2)); emit_insn (gen_avx_vec_concatv16si (operands[0], r1, r2));
} }
else else
......
gcc/testsuite/ChangeLog
2018-05-27 Jakub Jelinek <jakub@redhat.com>
PR target/85918
* gcc.target/i386/avx512dq-pr85918.c: New test.
2018-05-25 Jim Wilson <jimw@sifive.com> 2018-05-25 Jim Wilson <jimw@sifive.com>
* gcc.target/riscv/interrupt-1.c: New. * gcc.target/riscv/interrupt-1.c: New.
......
gcc/testsuite/gcc.target/i386/avx512dq-pr85918.c 0 → 100644
/* PR target/85918 */
/* { dg-do compile } */
/* { dg-options "-O3 -mavx512dq -mavx512vl -fdump-tree-vect-details" } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
#define N 1024
long long ll[N];
unsigned long long ull[N];
double d[N];
void ll2d (void)
{
int i;
for (i = 0; i < N; i++)
d[i] = ll[i];
}
void ull2d (void)
{
int i;
for (i = 0; i < N; i++)
d[i] = ull[i];
}
void d2ll (void)
{
int i;
for (i = 0; i < N; i++)
ll[i] = d[i];
}
void d2ull (void)
{
int i;
for (i = 0; i < N; i++)
ull[i] = d[i];
}
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