Skip to content

R
riscv-gcc-1
Commit 70ae0191 by David Edelsohn Committed by David Edelsohn
Options

re PR rtl-optimization/10588 ([PPC] i==0||j==0 should use cntlzw and srawi) 

	* config/rs6000/rs6000.md (call_indirect_nonlocal_aix32): Prefer
	CTR to LR.
	(call_indirect_nonlocal_aix64): Same.
	(call_value_indirect_nonlocal_aix32): Same.
	(call_value_indirect_nonlocal_aix64): Same.

	PR target/10588
	(eq): Use CLZ splitter for compare with zero.

From-SVN: r100759
parent 625b02b2
Showing with 66 additions and 20 deletions
gcc/ChangeLog
2005-06-08 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.md (call_indirect_nonlocal_aix32): Prefer
CTR to LR.
(call_indirect_nonlocal_aix64): Same.
(call_value_indirect_nonlocal_aix32): Same.
(call_value_indirect_nonlocal_aix64): Same.
PR target/10588
(eq): Use CLZ splitter for compare with zero.
2005-06-08 Bernd Schmidt <bernd.schmidt@analog.com> 2005-06-08 Bernd Schmidt <bernd.schmidt@analog.com>
* config/bfin/bfin.c (bfin_return_in_memory): Simplify; return * config/bfin/bfin.c (bfin_return_in_memory): Simplify; return
......
gcc/config/rs6000/rs6000.md
...@@ -10247,13 +10247,13 @@ ...@@ -10247,13 +10247,13 @@
;; and < 0 if they were not. ;; and < 0 if they were not.
(define_insn "*call_indirect_nonlocal_aix32" (define_insn "*call_indirect_nonlocal_aix32"
[(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
(match_operand 1 "" "g")) (match_operand 1 "" "g,g"))
(use (reg:SI 2)) (use (reg:SI 2))
(use (reg:SI 11)) (use (reg:SI 11))
(set (reg:SI 2) (set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20)))) (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
(clobber (match_scratch:SI 2 "=l"))] (clobber (match_scratch:SI 2 "=l,l"))]
"TARGET_32BIT && DEFAULT_ABI == ABI_AIX" "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
"b%T0l\;{l|lwz} 2,20(1)" "b%T0l\;{l|lwz} 2,20(1)"
[(set_attr "type" "jmpreg") [(set_attr "type" "jmpreg")
...@@ -10272,13 +10272,13 @@ ...@@ -10272,13 +10272,13 @@
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "*call_indirect_nonlocal_aix64" (define_insn "*call_indirect_nonlocal_aix64"
[(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
(match_operand 1 "" "g")) (match_operand 1 "" "g,g"))
(use (reg:DI 2)) (use (reg:DI 2))
(use (reg:DI 11)) (use (reg:DI 11))
(set (reg:DI 2) (set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40)))) (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
(clobber (match_scratch:SI 2 "=l"))] (clobber (match_scratch:SI 2 "=l,l"))]
"TARGET_64BIT && DEFAULT_ABI == ABI_AIX" "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
"b%T0l\;ld 2,40(1)" "b%T0l\;ld 2,40(1)"
[(set_attr "type" "jmpreg") [(set_attr "type" "jmpreg")
...@@ -10298,13 +10298,13 @@ ...@@ -10298,13 +10298,13 @@
(define_insn "*call_value_indirect_nonlocal_aix32" (define_insn "*call_value_indirect_nonlocal_aix32"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
(call (mem:SI (match_operand:SI 1 "register_operand" "cl")) (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
(match_operand 2 "" "g"))) (match_operand 2 "" "g,g")))
(use (reg:SI 2)) (use (reg:SI 2))
(use (reg:SI 11)) (use (reg:SI 11))
(set (reg:SI 2) (set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20)))) (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
(clobber (match_scratch:SI 3 "=l"))] (clobber (match_scratch:SI 3 "=l,l"))]
"TARGET_32BIT && DEFAULT_ABI == ABI_AIX" "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
"b%T1l\;{l|lwz} 2,20(1)" "b%T1l\;{l|lwz} 2,20(1)"
[(set_attr "type" "jmpreg") [(set_attr "type" "jmpreg")
...@@ -10325,13 +10325,13 @@ ...@@ -10325,13 +10325,13 @@
(define_insn "*call_value_indirect_nonlocal_aix64" (define_insn "*call_value_indirect_nonlocal_aix64"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
(call (mem:SI (match_operand:DI 1 "register_operand" "cl")) (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
(match_operand 2 "" "g"))) (match_operand 2 "" "g,g")))
(use (reg:DI 2)) (use (reg:DI 2))
(use (reg:DI 11)) (use (reg:DI 11))
(set (reg:DI 2) (set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40)))) (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
(clobber (match_scratch:SI 3 "=l"))] (clobber (match_scratch:SI 3 "=l,l"))]
"TARGET_64BIT && DEFAULT_ABI == ABI_AIX" "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
"b%T1l\;ld 2,40(1)" "b%T1l\;ld 2,40(1)"
[(set_attr "type" "jmpreg") [(set_attr "type" "jmpreg")
...@@ -11472,11 +11472,11 @@ ...@@ -11472,11 +11472,11 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] (clobber (match_scratch:SI 3 "=r,X,r,r,r"))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "@
xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 #
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
...@@ -11487,17 +11487,31 @@ ...@@ -11487,17 +11487,31 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
(eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
(clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] (clobber (match_scratch:DI 3 "=r,X,r,r,r"))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
subfic %3,%1,0\;adde %0,%3,%1 #
xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
[(set_attr "type" "three,two,three,three,three") [(set_attr "type" "three,two,three,three,three")
(set_attr "length" "12,8,12,12,12")]) (set_attr "length" "12,8,12,12,12")])
(define_split
[(set (match_operand:GPR 0 "gpc_reg_operand" "")
(eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
(match_operand:GPR 2 "zero_constant" "")))
(clobber (match_scratch:GPR 3 ""))]
""
[(set (match_dup 0)
(clz:GPR (match_dup 1)))
(set (match_dup 0)
(lshiftrt:GPR (match_dup 0) (match_dup 4)))]
{
operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
})
(define_insn "" (define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
(compare:CC (compare:CC
...@@ -11506,11 +11520,11 @@ ...@@ -11506,11 +11520,11 @@
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
(eq:SI (match_dup 1) (match_dup 2))) (eq:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] (clobber (match_scratch:SI 3 "=r,X,r,r,r,r,X,r,r,r"))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "@
xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
{sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 #
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
...@@ -11548,11 +11562,11 @@ ...@@ -11548,11 +11562,11 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
(eq:DI (match_dup 1) (match_dup 2))) (eq:DI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] (clobber (match_scratch:DI 3 "=r,X,r,r,r,r,X,r,r,r"))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
subfic %3,%1,0\;adde. %0,%3,%1 #
xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
...@@ -11582,6 +11596,27 @@ ...@@ -11582,6 +11596,27 @@
(const_int 0)))] (const_int 0)))]
"") "")
(define_split
[(set (match_operand:CC 4 "cc_reg_operand" "")
(compare:CC
(eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
(match_operand:GPR 2 "zero_constant" ""))
(const_int 0)))
(set (match_operand:GPR 0 "gpc_reg_operand" "")
(eq:GPR (match_dup 1) (match_dup 2)))
(clobber (match_scratch:GPR 3 ""))]
""
[(set (match_dup 0)
(clz:GPR (match_dup 1)))
(parallel [(set (match_dup 4)
(compare:CC (lshiftrt:GPR (match_dup 0) (match_dup 5))
(const_int 0)))
(set (match_dup 0)
(lshiftrt:GPR (match_dup 0) (match_dup 5)))])]
{
operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
})
;; We have insns of the form shown by the first define_insn below. If ;; We have insns of the form shown by the first define_insn below. If
;; there is something inside the comparison operation, we must split it. ;; there is something inside the comparison operation, we must split it.
(define_split (define_split
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment