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riscv-gcc-1
Commit 6fcd3a13 by DJ Delorie Committed by DJ Delorie
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rl78.c: Various whitespace and comment tweaks. 

* config/rl78/rl78.c: Various whitespace and comment tweaks.
(need_to_save): Save bank 0 on interrupts.
(characterize_address): Strip far address wrappers.
(rl78_as_legitimate_address): Likewise.
(transcode_memory_rtx): Likewise.
(rl78_peep_movhi_p): Disable this peephole after devirt.
(rl78_propogate_register_origins): Forget all origins when a
CLOBBER is seen.
* config/rl78/rl78-virt.md: Various whitespace tweaks.
* config/rl78/rl78-real.md: Various whitespace tweaks.  Additional
peephole2's.
* config/rl78/rl78.md (sel_rb): Disable for G10 just in case.
* config/rl78/rl78-expand.md (movqi): Check for subregs of consts.
* config/rl78/rl78.h (LINK_SPEC): Pass -gc-sections unless
relocating.
* config/rl78/constraints.md: Various whitespace and paren tweaks.

Co-Authored-By: Nick Clifton <nickc@redhat.com>

From-SVN: r202801
parent 4a08db33
Showing with 179 additions and 97 deletions
gcc/ChangeLog
2013-09-20 DJ Delorie <dj@redhat.com>
Nick Clifton <nickc@redhat.com>
* config/rl78/rl78.c: Various whitespace and comment tweaks.
(need_to_save): Save bank 0 on interrupts.
(characterize_address): Strip far address wrappers.
(rl78_as_legitimate_address): Likewise.
(transcode_memory_rtx): Likewise.
(rl78_peep_movhi_p): Disable this peephole after devirt.
(rl78_propogate_register_origins): Forget all origins when a
CLOBBER is seen.
* config/rl78/rl78-virt.md: Various whitespace tweaks.
* config/rl78/rl78-real.md: Various whitespace tweaks. Additional
peephole2's.
* config/rl78/rl78.md (sel_rb): Disable for G10 just in case.
* config/rl78/rl78-expand.md (movqi): Check for subregs of consts.
* config/rl78/rl78.h (LINK_SPEC): Pass -gc-sections unless
relocating.
* config/rl78/constraints.md: Various whitespace and paren tweaks.
2013-09-20 John David Anglin <danglin@gcc.gnu.org> 2013-09-20 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.md: In "scc" insn patterns, change output template to * config/pa/pa.md: In "scc" insn patterns, change output template to
......
gcc/config/rl78/constraints.md
...@@ -62,11 +62,13 @@ ...@@ -62,11 +62,13 @@
Integer constant equal to 8." Integer constant equal to 8."
(and (match_code "const_int") (and (match_code "const_int")
(match_test "IN_RANGE (ival, 8, 8)"))) (match_test "IN_RANGE (ival, 8, 8)")))
(define_constraint "Iv16" (define_constraint "Iv16"
"@internal "@internal
Integer constant equal to 16." Integer constant equal to 16."
(and (match_code "const_int") (and (match_code "const_int")
(match_test "IN_RANGE (ival, 16, 16)"))) (match_test "IN_RANGE (ival, 16, 16)")))
(define_constraint "Iv24" (define_constraint "Iv24"
"@internal "@internal
Integer constant equal to 24." Integer constant equal to 24."
...@@ -78,11 +80,13 @@ ...@@ -78,11 +80,13 @@
Integer constant in the range 9 @dots{} 15 (for shifts)." Integer constant in the range 9 @dots{} 15 (for shifts)."
(and (match_code "const_int") (and (match_code "const_int")
(match_test "IN_RANGE (ival, 9, 15)"))) (match_test "IN_RANGE (ival, 9, 15)")))
(define_constraint "Is17" (define_constraint "Is17"
"@internal "@internal
Integer constant in the range 17 @dots{} 23 (for shifts)." Integer constant in the range 17 @dots{} 23 (for shifts)."
(and (match_code "const_int") (and (match_code "const_int")
(match_test "IN_RANGE (ival, 17, 23)"))) (match_test "IN_RANGE (ival, 17, 23)")))
(define_constraint "Is25" (define_constraint "Is25"
"@internal "@internal
Integer constant in the range 25 @dots{} 31 (for shifts)." Integer constant in the range 25 @dots{} 31 (for shifts)."
...@@ -216,7 +220,7 @@ ...@@ -216,7 +220,7 @@
) )
(define_memory_constraint "Wab" (define_memory_constraint "Wab"
"es:[addr]" "es:[addr]"
(match_test "rl78_es_addr (op) && satisfies_constraint_Cab (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Cab (rl78_es_base (op)))
|| satisfies_constraint_Cab (op)") || satisfies_constraint_Cab (op)")
) )
...@@ -234,7 +238,7 @@ ...@@ -234,7 +238,7 @@
) )
(define_memory_constraint "Wbc" (define_memory_constraint "Wbc"
"es:word16[BC]" "es:word16[BC]"
(match_test "rl78_es_addr (op) && satisfies_constraint_Cbc (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Cbc (rl78_es_base (op)))
|| satisfies_constraint_Cbc (op)") || satisfies_constraint_Cbc (op)")
) )
...@@ -246,7 +250,7 @@ ...@@ -246,7 +250,7 @@
) )
(define_memory_constraint "Wde" (define_memory_constraint "Wde"
"es:[DE]" "es:[DE]"
(match_test "rl78_es_addr (op) && satisfies_constraint_Cde (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Cde (rl78_es_base (op)))
|| satisfies_constraint_Cde (op)") || satisfies_constraint_Cde (op)")
) )
...@@ -258,7 +262,7 @@ ...@@ -258,7 +262,7 @@
) )
(define_memory_constraint "Wca" (define_memory_constraint "Wca"
"es:[AX..HL] for calls" "es:[AX..HL] for calls"
(match_test "rl78_es_addr (op) && satisfies_constraint_Cca (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Cca (rl78_es_base (op)))
|| satisfies_constraint_Cca (op)") || satisfies_constraint_Cca (op)")
) )
...@@ -266,11 +270,11 @@ ...@@ -266,11 +270,11 @@
"[AX..HL,r8-r31] for calls" "[AX..HL,r8-r31] for calls"
(and (match_code "mem") (and (match_code "mem")
(and (match_code "reg" "0") (and (match_code "reg" "0")
(match_test "REGNO (XEXP (op, 0)) < 31"))) (match_test "REGNO (XEXP (op, 0)) < 32")))
) )
(define_memory_constraint "Wcv" (define_memory_constraint "Wcv"
"es:[AX..HL,r8-r23] for calls" "es:[AX..HL,r8-r31] for calls"
(match_test "rl78_es_addr (op) && satisfies_constraint_Ccv (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Ccv (rl78_es_base (op)))
|| satisfies_constraint_Ccv (op)") || satisfies_constraint_Ccv (op)")
) )
...@@ -288,7 +292,7 @@ ...@@ -288,7 +292,7 @@
) )
(define_memory_constraint "Wd2" (define_memory_constraint "Wd2"
"es:word16[DE]" "es:word16[DE]"
(match_test "rl78_es_addr (op) && satisfies_constraint_Cd2 (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Cd2 (rl78_es_base (op)))
|| satisfies_constraint_Cd2 (op)") || satisfies_constraint_Cd2 (op)")
) )
...@@ -300,7 +304,7 @@ ...@@ -300,7 +304,7 @@
) )
(define_memory_constraint "Whl" (define_memory_constraint "Whl"
"es:[HL]" "es:[HL]"
(match_test "rl78_es_addr (op) && satisfies_constraint_Chl (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Chl (rl78_es_base (op)))
|| satisfies_constraint_Chl (op)") || satisfies_constraint_Chl (op)")
) )
...@@ -314,7 +318,7 @@ ...@@ -314,7 +318,7 @@
) )
(define_memory_constraint "Wh1" (define_memory_constraint "Wh1"
"es:byte8[HL]" "es:byte8[HL]"
(match_test "rl78_es_addr (op) && satisfies_constraint_Ch1 (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Ch1 (rl78_es_base (op)))
|| satisfies_constraint_Ch1 (op)") || satisfies_constraint_Ch1 (op)")
) )
...@@ -325,7 +329,7 @@ ...@@ -325,7 +329,7 @@
) )
(define_memory_constraint "Whb" (define_memory_constraint "Whb"
"es:[HL+B]" "es:[HL+B]"
(match_test "rl78_es_addr (op) && satisfies_constraint_Chb (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Chb (rl78_es_base (op)))
|| satisfies_constraint_Chb (op)") || satisfies_constraint_Chb (op)")
) )
...@@ -343,7 +347,7 @@ ...@@ -343,7 +347,7 @@
) )
(define_memory_constraint "Ws1" (define_memory_constraint "Ws1"
"es:word8[SP]" "es:word8[SP]"
(match_test "rl78_es_addr (op) && satisfies_constraint_Cs1 (rl78_es_base (op)) (match_test "(rl78_es_addr (op) && satisfies_constraint_Cs1 (rl78_es_base (op)))
|| satisfies_constraint_Cs1 (op)") || satisfies_constraint_Cs1 (op)")
) )
......
gcc/config/rl78/rl78-expand.md
...@@ -43,14 +43,6 @@ ...@@ -43,14 +43,6 @@
&& GET_CODE (XEXP (XEXP (XEXP (operand1, 0), 0), 0)) == SYMBOL_REF) && GET_CODE (XEXP (XEXP (XEXP (operand1, 0), 0), 0)) == SYMBOL_REF)
FAIL; FAIL;
/* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))).
cf. g++.dg/abi/packed.C. */
if (GET_CODE (operand1) == SUBREG
&& GET_CODE (XEXP (operand1, 0)) == CONST
&& GET_CODE (XEXP (XEXP (operand1, 0), 0)) == PLUS
&& GET_CODE (XEXP (XEXP (XEXP (operand1, 0), 0), 0)) == SYMBOL_REF)
FAIL;
if (CONST_INT_P (operand1) && ! IN_RANGE (INTVAL (operand1), (-1 << 8) + 1, (1 << 8) - 1)) if (CONST_INT_P (operand1) && ! IN_RANGE (INTVAL (operand1), (-1 << 8) + 1, (1 << 8) - 1))
FAIL; FAIL;
} }
......
gcc/config/rl78/rl78-real.md
...@@ -312,7 +312,7 @@ ...@@ -312,7 +312,7 @@
call\t%A1" call\t%A1"
) )
(define_insn "cbranchqi4_real_signed" (define_insn "*cbranchqi4_real_signed"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator_signed" (match_operator 0 "rl78_cmp_operator_signed"
[(match_operand:QI 1 "general_operand" "A,A,A") [(match_operand:QI 1 "general_operand" "A,A,A")
...@@ -326,7 +326,6 @@ ...@@ -326,7 +326,6 @@
cmp\t%1, %2 \;xor1 CY,%1.7\;xor1 CY,%2.7\;sk%c0 \;br\t!!%3" cmp\t%1, %2 \;xor1 CY,%1.7\;xor1 CY,%2.7\;sk%c0 \;br\t!!%3"
) )
(define_insn "*cbranchqi4_real" (define_insn "*cbranchqi4_real"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator_real" (match_operator 0 "rl78_cmp_operator_real"
...@@ -342,7 +341,7 @@ ...@@ -342,7 +341,7 @@
cmp\t%1, %2 \;sk%c0 \;br\t!!%3" cmp\t%1, %2 \;sk%c0 \;br\t!!%3"
) )
(define_insn "cbranchhi4_real_signed" (define_insn "*cbranchhi4_real_signed"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator_signed" (match_operator 0 "rl78_cmp_operator_signed"
[(match_operand:HI 1 "general_operand" "A,A,A,vR") [(match_operand:HI 1 "general_operand" "A,A,A,vR")
...@@ -381,7 +380,7 @@ ...@@ -381,7 +380,7 @@
"cmpw\t%1, %2 \;sk%c0 \;br\t!!%3" "cmpw\t%1, %2 \;sk%c0 \;br\t!!%3"
) )
(define_insn "cbranchsi4_real_lt" (define_insn "*cbranchsi4_real_lt"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(lt (match_operand:SI 0 "general_operand" "U,vWabWhlWh1") (lt (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
(const_int 0)) (const_int 0))
...@@ -395,7 +394,7 @@ ...@@ -395,7 +394,7 @@
mov1 CY,%E0.7 \;sknc \;br\t!!%1" mov1 CY,%E0.7 \;sknc \;br\t!!%1"
) )
(define_insn "cbranchsi4_real_ge" (define_insn "*cbranchsi4_real_ge"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(ge (match_operand:SI 0 "general_operand" "U,vWabWhlWh1") (ge (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
(const_int 0)) (const_int 0))
...@@ -409,7 +408,7 @@ ...@@ -409,7 +408,7 @@
mov1 CY,%E0.7 \;skc \;br\t!!%1" mov1 CY,%E0.7 \;skc \;br\t!!%1"
) )
(define_insn "cbranchsi4_real_signed" (define_insn "*cbranchsi4_real_signed"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator_signed" (match_operator 0 "rl78_cmp_operator_signed"
[(match_operand:SI 1 "nonimmediate_operand" "vU,vU,vU") [(match_operand:SI 1 "nonimmediate_operand" "vU,vU,vU")
...@@ -425,7 +424,7 @@ ...@@ -425,7 +424,7 @@
movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%c0 \;br\t!!%3" movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%c0 \;br\t!!%3"
) )
(define_insn "cbranchsi4_real" (define_insn "*cbranchsi4_real"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator_real" (match_operator 0 "rl78_cmp_operator_real"
[(match_operand:SI 1 "general_operand" "vUi") [(match_operand:SI 1 "general_operand" "vUi")
...@@ -491,26 +490,62 @@ ...@@ -491,26 +490,62 @@
;; in the peephole not matching and the optimization being missed. ;; in the peephole not matching and the optimization being missed.
(define_peephole2 (define_peephole2
[(set (match_operand:QI 1 "register_operand") (reg:QI A_REG)) [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
(set (match_dup 1) (and:QI (match_dup 1) (match_operand 2 "immediate_operand"))) (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
(set (pc) (if_then_else (eq (match_dup 1) (const_int 0)) (set (pc) (if_then_else (eq (match_dup 0) (const_int 0))
(label_ref (match_operand 3 "")) (label_ref (match_operand 2 ""))
(pc)))]
"peep2_regno_dead_p (3, REGNO (operands[0]))
&& exact_log2 (INTVAL (operands[1])) >= 0"
[(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
(label_ref (match_dup 2))
(pc)))] (pc)))]
"peep2_regno_dead_p (3, REGNO (operands[1]))
&& exact_log2 (INTVAL (operands[2])) >= 0"
[(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 2)) (const_int 0))
(label_ref (match_dup 3)) (pc)))]
) )
(define_peephole2 (define_peephole2
[(set (match_operand:QI 1 "register_operand") (reg:QI A_REG)) [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
(set (match_dup 1) (and:QI (match_dup 1) (match_operand 2 "immediate_operand"))) (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
(set (pc) (if_then_else (ne (match_dup 1) (const_int 0)) (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
(label_ref (match_operand 3 "")) (label_ref (match_operand 2 ""))
(pc)))] (pc)))]
"peep2_regno_dead_p (3, REGNO (operands[1])) "peep2_regno_dead_p (3, REGNO (operands[0]))
&& exact_log2 (INTVAL (operands[2])) >= 0" && exact_log2 (INTVAL (operands[1])) >= 0"
[(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 2)) (const_int 0)) [(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
(label_ref (match_dup 3)) (pc)))] (label_ref (match_dup 2))
(pc)))]
)
;; Eliminate needless register copies.
(define_peephole2
[(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand"))
(set (match_operand:HI 2 "register_operand") (match_dup 0))]
"peep2_regno_dead_p (2, REGNO (operands[0]))
&& (REGNO (operands[1]) < 8 || REGNO (operands[2]) < 8)"
[(set (match_dup 2) (match_dup 1))]
)
;; Eliminate needless register copying when performing bit manipulations.
(define_peephole2
[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
(set (match_dup 0) (ior:QI (match_dup 0) (match_operand 1 "immediate_operand")))
(set (reg:QI A_REG) (match_dup 0))]
"peep2_regno_dead_p (3, REGNO (operands[0]))"
[(set (reg:QI A_REG) (ior:QI (reg:QI A_REG) (match_dup 1)))]
)
(define_peephole2
[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
(set (match_dup 0) (xor:QI (match_dup 0) (match_operand 1 "immediate_operand")))
(set (reg:QI A_REG) (match_dup 0))]
"peep2_regno_dead_p (3, REGNO (operands[0]))"
[(set (reg:QI A_REG) (xor:QI (reg:QI A_REG) (match_dup 1)))]
)
(define_peephole2
[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
(set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
(set (reg:QI A_REG) (match_dup 0))]
"peep2_regno_dead_p (3, REGNO (operands[0]))"
[(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))]
) )
gcc/config/rl78/rl78-virt.md
...@@ -312,7 +312,7 @@ ...@@ -312,7 +312,7 @@
[(set_attr "valloc" "op1")] [(set_attr "valloc" "op1")]
) )
(define_insn "cbranchqi4_virt_signed" (define_insn "*cbranchqi4_virt_signed"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator_signed" (match_operator 0 "rl78_cmp_operator_signed"
[(match_operand:QI 1 "general_operand" "vim") [(match_operand:QI 1 "general_operand" "vim")
...@@ -336,7 +336,7 @@ ...@@ -336,7 +336,7 @@
[(set_attr "valloc" "cmp")] [(set_attr "valloc" "cmp")]
) )
(define_insn "cbranchhi4_virt_signed" (define_insn "*cbranchhi4_virt_signed"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator_signed" (match_operator 0 "rl78_cmp_operator_signed"
[(match_operand:HI 1 "general_operand" "vim") [(match_operand:HI 1 "general_operand" "vim")
...@@ -360,7 +360,7 @@ ...@@ -360,7 +360,7 @@
[(set_attr "valloc" "cmp")] [(set_attr "valloc" "cmp")]
) )
(define_insn "cbranchsi4_virt" (define_insn "*cbranchsi4_virt"
[(set (pc) (if_then_else [(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator" (match_operator 0 "rl78_cmp_operator"
[(match_operand:SI 1 "general_operand" "vim") [(match_operand:SI 1 "general_operand" "vim")
......
gcc/config/rl78/rl78.h
...@@ -52,6 +52,7 @@ ...@@ -52,6 +52,7 @@
#undef LINK_SPEC #undef LINK_SPEC
#define LINK_SPEC "\ #define LINK_SPEC "\
%{mrelax:-relax} \ %{mrelax:-relax} \
%{!r:--gc-sections} \
" "
#undef LIB_SPEC #undef LIB_SPEC
......
gcc/config/rl78/rl78.md
...@@ -142,7 +142,7 @@ ...@@ -142,7 +142,7 @@
(define_insn "sel_rb" (define_insn "sel_rb"
[(unspec_volatile [(match_operand 0 "immediate_operand" "")] UNS_SET_RB)] [(unspec_volatile [(match_operand 0 "immediate_operand" "")] UNS_SET_RB)]
"" "!TARGET_G10"
"sel\trb%u0" "sel\trb%u0"
) )
......
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