Commit 6f54921d by Jeff Law

mn10300.md (udivmodhi4, divmodhi4): Remove expander, give corresponding pattern [u]divmodhir4 name.

        * mn10300.md (udivmodhi4, divmodhi4): Remove expander, give
        corresponding pattern [u]divmodhir4 name.  Clear MDR register
        in the udivmodhi4 pattern itself.
        (clear_mdr): Delete pattern.

From-SVN: r14058
parent f0dc3f49
...@@ -775,29 +775,20 @@ ...@@ -775,29 +775,20 @@
"mul %2,%0" "mul %2,%0"
[(set_attr "cc" "set_zn")]) [(set_attr "cc" "set_zn")])
(define_expand "udivmodsi4" (define_insn "udivmodsi4"
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" "")))
(set (match_operand:SI 3 "register_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])]
""
"
{
rtx reg = gen_reg_rtx (SImode);
emit_move_insn (reg, GEN_INT (0));
emit_insn (gen_clear_mdr (reg));
}")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d") [(set (match_operand:SI 0 "general_operand" "=d")
(udiv:SI (match_operand:SI 1 "general_operand" "0") (udiv:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "d"))) (match_operand:SI 2 "general_operand" "d")))
(set (match_operand:SI 3 "general_operand" "=d") (set (match_operand:SI 3 "general_operand" "=&d")
(umod:SI (match_dup 1) (match_dup 2)))] (umod:SI (match_dup 1) (match_dup 2)))]
"" ""
"* "*
{ {
if (zero_dreg)
output_asm_insn (\"mov %0,mdr\", &zero_dreg);
else
output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
if (find_reg_note (insn, REG_UNUSED, operands[3])) if (find_reg_note (insn, REG_UNUSED, operands[3]))
return \"divu %2,%0\"; return \"divu %2,%0\";
else else
...@@ -805,16 +796,7 @@ ...@@ -805,16 +796,7 @@
}" }"
[(set_attr "cc" "set_zn")]) [(set_attr "cc" "set_zn")])
(define_expand "divmodsi4" (define_insn "divmodsi4"
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" "")))
(set (match_operand:SI 3 "register_operand" "")
(mod:SI (match_dup 1) (match_dup 2)))])]
""
"")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d") [(set (match_operand:SI 0 "general_operand" "=d")
(div:SI (match_operand:SI 1 "general_operand" "0") (div:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "d"))) (match_operand:SI 2 "general_operand" "d")))
...@@ -830,12 +812,6 @@ ...@@ -830,12 +812,6 @@
}" }"
[(set_attr "cc" "set_zn")]) [(set_attr "cc" "set_zn")])
(define_insn "clear_mdr"
[(unspec_volatile [(const_int 2)] 0)
(use (match_operand:SI 0 "register_operand" "d"))]
""
"mov %0,mdr"
[(set_attr "cc" "none")])
;; ---------------------------------------------------------------------- ;; ----------------------------------------------------------------------
;; AND INSTRUCTIONS ;; AND INSTRUCTIONS
......
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