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riscv-gcc-1
Commit 6f317ef3 by Kazu Hirata Committed by Kazu Hirata
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darwin-tramp.asm: Fix comment formatting. 

	* config/rs6000/darwin-tramp.asm: Fix comment formatting.
	* config/rs6000/freebsd.h: Likewise.
	* config/rs6000/rs6000.c: Likewise.
	* config/sh/sh.c: Likewise.
	* config/sh/sh.h: Likewise.

From-SVN: r48362
parent fac51051
Showing with 31 additions and 23 deletions
gcc/ChangeLog
2001-12-29 Kazu Hirata <kazu@hxi.com>
* config/rs6000/darwin-tramp.asm: Fix comment formatting.
* config/rs6000/freebsd.h: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.h: Likewise.
2001-12-28 Stan Shebs <shebs@apple.com>
* objc/objc-act.c (build_module_descriptor): Make sure the init
......
gcc/config/rs6000/darwin-tramp.asm
......@@ -33,7 +33,7 @@
* executable file might be covered by the GNU General Public License.
*/
/* Set up trampolines. */
/* Set up trampolines. */
.text
.align 2
......
gcc/config/rs6000/freebsd.h
......@@ -18,7 +18,7 @@ You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
/* Override the defaults, which exist to force the proper definition. */
/* Override the defaults, which exist to force the proper definition. */
#undef CPP_OS_DEFAULT_SPEC
#define CPP_OS_DEFAULT_SPEC "%(cpp_os_freebsd)"
......
gcc/config/rs6000/rs6000.c
......@@ -722,7 +722,7 @@ xer_operand (op, mode)
}
/* Return 1 if OP is a signed 8-bit constant. Int multiplication
by such constants completes more quickly. */
by such constants completes more quickly. */
int
s8bit_cint_operand (op, mode)
......@@ -1813,7 +1813,7 @@ rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win)
&& GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
{
/* Result of previous invocation of this function on Darwin
floating point constant. */
floating point constant. */
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
opnum, (enum reload_type)type);
......@@ -3982,7 +3982,7 @@ altivec_init_builtins (void)
def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pchar, ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
/* Add the simple ternary operators. */
/* Add the simple ternary operators. */
d = (struct builtin_description *) bdesc_3arg;
for (i = 0; i < sizeof (bdesc_3arg) / sizeof *d; i++, d++)
{
......@@ -4280,7 +4280,7 @@ expand_block_move (operands)
return 1;
/* store_one_arg depends on expand_block_move to handle at least the size of
reg_parm_stack_space. */
reg_parm_stack_space. */
if (bytes > (TARGET_POWERPC64 ? 64 : 32))
return 0;
......
gcc/config/sh/sh.c
......@@ -80,7 +80,7 @@ int pragma_nosave_low_regs;
sh_expand_prologue. */
int current_function_anonymous_args;
/* Global variables for machine-dependent things. */
/* Global variables for machine-dependent things. */
/* Which cpu are we scheduling for. */
enum processor_type sh_cpu;
......@@ -1455,7 +1455,7 @@ shl_and_kind (left_rtx, mask_rtx, attrp)
continue;
}
/* ??? Could try to put zero extend into initial right shift,
or even shift a bit left before the right shift. */
or even shift a bit left before the right shift. */
/* Determine value of first part of left shift, to get to the
zero extend cut-off point. */
first = width - exact_log2 (lsb2) + right;
......@@ -3236,7 +3236,7 @@ machine_dependent_reorg (first)
entirely reliable around libcalls;
newlib/libm/math/e_pow.c is a test case. Sometimes
an insn will appear in LOG_LINKS even though it is
not the most recent insn which sets the register. */
not the most recent insn which sets the register. */
if (foundinsn
&& (scanset
......@@ -3846,7 +3846,7 @@ output_stack_adjust (size, reg, temp)
emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
/* Try to do it with two partial adjustments; however, we must make
sure that the stack is properly aligned at all times, in case
an interrupt occurs between the two partial adjustments. */
an interrupt occurs between the two partial adjustments. */
else if (CONST_OK_FOR_I (size / 2 & -4)
&& CONST_OK_FOR_I (size - (size / 2 & -4)))
{
......@@ -4082,7 +4082,7 @@ sh_expand_prologue ()
extra_push = 0;
/* This is set by SETUP_VARARGS to indicate that this is a varargs
routine. Clear it here so that the next function isn't affected. */
routine. Clear it here so that the next function isn't affected. */
if (current_function_anonymous_args)
{
current_function_anonymous_args = 0;
......@@ -4268,7 +4268,7 @@ sh_builtin_saveregs ()
int bufsize, regno;
HOST_WIDE_INT alias_set;
/* Allocate block of memory for the regs. */
/* Allocate block of memory for the regs. */
/* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
Or can assign_stack_local accept a 0 SIZE argument? */
bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
......@@ -5509,7 +5509,7 @@ nonpic_symbol_mentioned_p (x)
}
/* Convert a non-PIC address in `orig' to a PIC address using @GOT or
@GOTOFF in `reg'. */
@GOTOFF in `reg'. */
rtx
legitimize_pic_address (orig, mode, reg)
rtx orig;
......
gcc/config/sh/sh.h
......@@ -164,10 +164,10 @@ extern int target_flags;
/* Nonzero if we should generate code using type 3E insns. */
#define TARGET_SH3E (target_flags & SH3E_BIT)
/* Nonzero if the cache line size is 32. */
/* Nonzero if the cache line size is 32. */
#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT)
/* Nonzero if we schedule for a superscalar implementation. */
/* Nonzero if we schedule for a superscalar implementation. */
#define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
/* Nonzero if the target has separate instruction and data caches. */
......@@ -430,7 +430,7 @@ do { \
&& GET_CODE (PREV_INSN (A_LABEL)) == INSN \
&& GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
&& XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
/* explicit alignment insn in constant tables. */ \
/* explicit alignment insn in constant tables. */ \
? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
: 0)
......@@ -998,7 +998,7 @@ extern const enum reg_class reg_class_from_letter[];
((TYPE) != 0 \
&& (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
|| TREE_ADDRESSABLE (TYPE)))
/* Some subroutine macros specific to this machine. */
/* Some subroutine macros specific to this machine. */
#define BASE_RETURN_VALUE_REG(MODE) \
((TARGET_SH3E && ((MODE) == SFmode)) \
......@@ -1046,7 +1046,7 @@ extern const enum reg_class reg_class_from_letter[];
#define LIBCALL_VALUE(MODE) \
gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
/* 1 if N is a possible register number for a function value. */
/* 1 if N is a possible register number for a function value. */
#define FUNCTION_VALUE_REGNO_P(REGNO) \
((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
......@@ -1134,7 +1134,7 @@ struct sh_args {
: ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
/* Return boolean indicating arg of mode MODE will be passed in a reg.
This macro is only used in this file. */
This macro is only used in this file. */
#define PASS_IN_REG_P(CUM, MODE, TYPE) \
(((TYPE) == 0 \
......@@ -1642,7 +1642,7 @@ extern int current_function_anonymous_args;
/* Define as C expression which evaluates to nonzero if the tablejump
instruction expects the table to contain offsets from the address of the
table.
Do not define this if the table should contain absolute addresses. */
Do not define this if the table should contain absolute addresses. */
#define CASE_VECTOR_PC_RELATIVE 1
/* Specify the tree operation to be used to convert reals to integers. */
......@@ -1916,7 +1916,7 @@ while (0)
specified as the number of bits.
Try to use function `asm_output_aligned_bss' defined in file
`varasm.c' when defining this macro. */
`varasm.c' when defining this macro. */
#ifndef ASM_OUTPUT_ALIGNED_BSS
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
......@@ -2021,11 +2021,11 @@ extern char fp_reg_names[][5];
assemble_name ((STREAM), (NAME)), \
fputc ('\n', (STREAM)))
/* The prefix to add to user-visible assembler symbols. */
/* The prefix to add to user-visible assembler symbols. */
#define USER_LABEL_PREFIX "_"
/* The prefix to add to an internally generated label. */
/* The prefix to add to an internally generated label. */
#define LOCAL_LABEL_PREFIX ""
......
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