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riscv-gcc-1
Commit 6e8b7d9c by Bill Schmidt Committed by William Schmidt
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vsx.md (*vsx_le_perm_load_v2di): Generalize to handle vector float as well. 

2013-10-11  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to
	handle vector float as well.
	(*vsx_le_perm_load_v4si): Likewise.
	(*vsx_le_perm_store_v2di): Likewise.
	(*vsx_le_perm_store_v4si): Likewise.

From-SVN: r203458
parent f200869a
Showing with 28 additions and 20 deletions
gcc/ChangeLog
2013-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com> 2013-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to
handle vector float as well.
(*vsx_le_perm_load_v4si): Likewise.
(*vsx_le_perm_store_v2di): Likewise.
(*vsx_le_perm_store_v4si): Likewise.
2013-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/vector.md (vec_realign_load<mode>): Generate vperm * config/rs6000/vector.md (vec_realign_load<mode>): Generate vperm
directly to circumvent subtract from splat{31} workaround. directly to circumvent subtract from splat{31} workaround.
* config/rs6000/rs6000-protos.h (altivec_expand_vec_perm_le): New * config/rs6000/rs6000-protos.h (altivec_expand_vec_perm_le): New
......
gcc/config/rs6000/vsx.md
...@@ -219,18 +219,18 @@ ...@@ -219,18 +219,18 @@
;; The patterns for LE permuted loads and stores come before the general ;; The patterns for LE permuted loads and stores come before the general
;; VSX moves so they match first. ;; VSX moves so they match first.
(define_insn_and_split "*vsx_le_perm_load_v2di" (define_insn_and_split "*vsx_le_perm_load_<mode>"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
(match_operand:V2DI 1 "memory_operand" "Z"))] (match_operand:VSX_D 1 "memory_operand" "Z"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX" "!BYTES_BIG_ENDIAN && TARGET_VSX"
"#" "#"
"!BYTES_BIG_ENDIAN && TARGET_VSX" "!BYTES_BIG_ENDIAN && TARGET_VSX"
[(set (match_dup 2) [(set (match_dup 2)
(vec_select:V2DI (vec_select:<MODE>
(match_dup 1) (match_dup 1)
(parallel [(const_int 1) (const_int 0)]))) (parallel [(const_int 1) (const_int 0)])))
(set (match_dup 0) (set (match_dup 0)
(vec_select:V2DI (vec_select:<MODE>
(match_dup 2) (match_dup 2)
(parallel [(const_int 1) (const_int 0)])))] (parallel [(const_int 1) (const_int 0)])))]
" "
...@@ -242,19 +242,19 @@ ...@@ -242,19 +242,19 @@
[(set_attr "type" "vecload") [(set_attr "type" "vecload")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn_and_split "*vsx_le_perm_load_v4si" (define_insn_and_split "*vsx_le_perm_load_<mode>"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=wa") [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
(match_operand:V4SI 1 "memory_operand" "Z"))] (match_operand:VSX_W 1 "memory_operand" "Z"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX" "!BYTES_BIG_ENDIAN && TARGET_VSX"
"#" "#"
"!BYTES_BIG_ENDIAN && TARGET_VSX" "!BYTES_BIG_ENDIAN && TARGET_VSX"
[(set (match_dup 2) [(set (match_dup 2)
(vec_select:V4SI (vec_select:<MODE>
(match_dup 1) (match_dup 1)
(parallel [(const_int 2) (const_int 3) (parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)]))) (const_int 0) (const_int 1)])))
(set (match_dup 0) (set (match_dup 0)
(vec_select:V4SI (vec_select:<MODE>
(match_dup 2) (match_dup 2)
(parallel [(const_int 2) (const_int 3) (parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))] (const_int 0) (const_int 1)])))]
...@@ -333,18 +333,18 @@ ...@@ -333,18 +333,18 @@
[(set_attr "type" "vecload") [(set_attr "type" "vecload")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn_and_split "*vsx_le_perm_store_v2di" (define_insn_and_split "*vsx_le_perm_store_<mode>"
[(set (match_operand:V2DI 0 "memory_operand" "=Z") [(set (match_operand:VSX_D 0 "memory_operand" "=Z")
(match_operand:V2DI 1 "vsx_register_operand" "+wa"))] (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX" "!BYTES_BIG_ENDIAN && TARGET_VSX"
"#" "#"
"!BYTES_BIG_ENDIAN && TARGET_VSX" "!BYTES_BIG_ENDIAN && TARGET_VSX"
[(set (match_dup 2) [(set (match_dup 2)
(vec_select:V2DI (vec_select:<MODE>
(match_dup 1) (match_dup 1)
(parallel [(const_int 1) (const_int 0)]))) (parallel [(const_int 1) (const_int 0)])))
(set (match_dup 0) (set (match_dup 0)
(vec_select:V2DI (vec_select:<MODE>
(match_dup 2) (match_dup 2)
(parallel [(const_int 1) (const_int 0)])))] (parallel [(const_int 1) (const_int 0)])))]
" "
...@@ -356,19 +356,19 @@ ...@@ -356,19 +356,19 @@
[(set_attr "type" "vecstore") [(set_attr "type" "vecstore")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn_and_split "*vsx_le_perm_store_v4si" (define_insn_and_split "*vsx_le_perm_store_<mode>"
[(set (match_operand:V4SI 0 "memory_operand" "=Z") [(set (match_operand:VSX_W 0 "memory_operand" "=Z")
(match_operand:V4SI 1 "vsx_register_operand" "+wa"))] (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX" "!BYTES_BIG_ENDIAN && TARGET_VSX"
"#" "#"
"!BYTES_BIG_ENDIAN && TARGET_VSX" "!BYTES_BIG_ENDIAN && TARGET_VSX"
[(set (match_dup 2) [(set (match_dup 2)
(vec_select:V4SI (vec_select:<MODE>
(match_dup 1) (match_dup 1)
(parallel [(const_int 2) (const_int 3) (parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)]))) (const_int 0) (const_int 1)])))
(set (match_dup 0) (set (match_dup 0)
(vec_select:V4SI (vec_select:<MODE>
(match_dup 2) (match_dup 2)
(parallel [(const_int 2) (const_int 3) (parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))] (const_int 0) (const_int 1)])))]
......
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