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Commit 6e755043 by Jeffrey A Law Committed by Jeff Law
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mn10300.c, [...]: Remove "global zero register" optimizations. 

        * mn10300.c, mn10300.h, mn10300.md: Remove "global zero register"
        optimizations.

From-SVN: r21686
parent 49e04385
Showing with 14 additions and 305 deletions
gcc/ChangeLog
Wed Aug 12 17:25:18 1998 Jeffrey A Law (law@cygnus.com)
* mn10300.c, mn10300.h, mn10300.md: Remove "global zero register"
optimizations.
Wed Aug 12 12:39:16 1998 Gavin Romig-Koch <gavin@cygnus.com>
* mips/mips.h (ENCODE_SECTION_INFO): Set SYMBOL_REF_FLAG for
......
gcc/config/mn10300/mn10300.c
......@@ -41,26 +41,6 @@ Boston, MA 02111-1307, USA. */
speed standpoint, so we want to optimize this sooner or later. */
#define REG_SAVE_BYTES (16)
/* Global registers known to hold the value zero.
Normally we'd depend on CSE and combine to put zero into a
register and re-use it.
However, on the mn10x00 processors we implicitly use the constant
zero in tst instructions, so we might be able to do better by
loading the value into a register in the prologue, then re-useing
that register throughout the function.
We could perform similar optimizations for other constants, but with
gcse due soon, it doesn't seem worth the effort.
These variables hold a rtx for a register known to hold the value
zero throughout the entire function, or NULL if no register of
the appropriate class has such a value throughout the life of the
function. */
rtx zero_dreg;
rtx zero_areg;
void
asm_file_start (file)
FILE *file;
......@@ -379,128 +359,11 @@ can_use_return_insn ()
&& !frame_pointer_needed);
}
/* Count the number of tst insns which compare a data or address
register with zero. */
static void
count_tst_insns (dreg_countp, areg_countp, oreg_countp)
int *dreg_countp;
int *areg_countp;
int *oreg_countp;
{
rtx insn;
/* Assume no tst insns exist. */
*dreg_countp = 0;
*areg_countp = 0;
*oreg_countp = 0;
/* If not optimizing, then quit now. */
if (!optimize)
return;
/* Walk through all the insns. */
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{
rtx pat;
/* Ignore anything that is not a normal INSN. */
if (GET_CODE (insn) != INSN)
continue;
/* Ignore anything that isn't a SET. */
pat = PATTERN (insn);
if (GET_CODE (pat) != SET)
continue;
/* Check for a tst insn. */
if (SET_DEST (pat) == cc0_rtx
&& GET_CODE (SET_SRC (pat)) == REG)
{
if (REGNO_REG_CLASS (REGNO (SET_SRC (pat))) == DATA_REGS)
(*dreg_countp)++;
if (REGNO_REG_CLASS (REGNO (SET_SRC (pat))) == ADDRESS_REGS)
(*areg_countp)++;
}
/* Setting an address register to zero can also be optimized,
so count it just like a tst insn. */
if (GET_CODE (SET_DEST (pat)) == REG
&& SET_SRC (pat) == CONST0_RTX (GET_MODE (SET_DEST (pat)))
&& REGNO_REG_CLASS (REGNO (SET_DEST (pat))) == ADDRESS_REGS)
(*areg_countp)++;
}
}
void
expand_prologue ()
{
unsigned int size;
/* We need to end the current sequence so that count_tst_insns can
look at all the insns in this function. Normally this would be
unsafe, but it's OK in the prologue/epilogue expanders. */
end_sequence ();
/* Determine if it is profitable to put the value zero into a register
for the entire function. If so, set ZERO_DREG and ZERO_AREG. */
if (regs_ever_live[2] || regs_ever_live[3]
|| regs_ever_live[6] || regs_ever_live[7]
|| frame_pointer_needed)
{
int dreg_count, areg_count, oreg_count;
/* Get a count of the number of tst insns which use address and
data registers. */
count_tst_insns (&dreg_count, &areg_count, &oreg_count);
/* If there's more than one tst insn using a data register, then
this optimization is a win. */
if ((dreg_count > 1 || oreg_count > 1)
&& (!regs_ever_live[2] || !regs_ever_live[3]))
{
if (!regs_ever_live[2])
{
regs_ever_live[2] = 1;
zero_dreg = gen_rtx (REG, SImode, 2);
}
else
{
regs_ever_live[3] = 1;
zero_dreg = gen_rtx (REG, SImode, 3);
}
}
else
zero_dreg = NULL_RTX;
/* If there's more than two tst insns using an address register,
then this optimization is a win. */
if ((areg_count > 2 || oreg_count > 1)
&& (!regs_ever_live[6] || !regs_ever_live[7]))
{
if (!regs_ever_live[6])
{
regs_ever_live[6] = 1;
zero_areg = gen_rtx (REG, SImode, 6);
}
else
{
regs_ever_live[7] = 1;
zero_areg = gen_rtx (REG, SImode, 7);
}
}
else
zero_areg = NULL_RTX;
}
else
{
zero_dreg = NULL_RTX;
zero_areg = NULL_RTX;
}
/* Start a new sequence. */
start_sequence ();
/* SIZE includes the fixed stack space needed for function calls. */
size = get_frame_size () + current_function_outgoing_args_size;
size += (current_function_outgoing_args_size ? 4 : 0);
......@@ -535,13 +398,6 @@ expand_prologue ()
emit_insn (gen_addsi3 (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (-size)));
/* Load zeros into registers as needed. */
if (zero_dreg)
emit_move_insn (zero_dreg, const0_rtx);
if (zero_areg)
emit_move_insn (zero_areg, const0_rtx);
}
void
......@@ -898,29 +754,6 @@ output_tst (operand, insn)
rtx temp;
int past_call = 0;
/* If we have a data register which is known to be zero throughout
the function, then use it instead of doing a search. */
if (zero_dreg && REGNO_REG_CLASS (REGNO (operand)) == DATA_REGS)
{
rtx xoperands[2];
xoperands[0] = operand;
xoperands[1] = zero_dreg;
output_asm_insn ("cmp %1,%0", xoperands);
return "";
}
/* Similarly for address registers. */
if (zero_areg && REGNO_REG_CLASS (REGNO (operand)) == ADDRESS_REGS)
{
rtx xoperands[2];
xoperands[0] = operand;
xoperands[1] = zero_areg;
output_asm_insn ("cmp %1,%0", xoperands);
return "";
}
/* We can save a byte if we can find a register which has the value
zero in it. */
temp = PREV_INSN (insn);
......
gcc/config/mn10300/mn10300.h
......@@ -36,10 +36,6 @@ Boston, MA 02111-1307, USA. */
extern int target_flags;
/* Global registers known to hold the value zero. */
extern struct rtx_def *zero_dreg;
extern struct rtx_def *zero_areg;
/* Macros used in the machine description to test the flags. */
/* Macro to define tables used to set the flags.
......
gcc/config/mn10300/mn10300.md
......@@ -71,20 +71,6 @@
case 2:
return \"clr %0\";
case 3:
if (zero_areg)
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg;
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %1,%0\", xoperands);
else
output_asm_insn (\"mov %1,%0\", xoperands);
return \"\";
}
/* FALLTHROUGH */
case 4:
case 5:
case 6:
......@@ -135,20 +121,6 @@
case 2:
return \"clr %0\";
case 3:
if (zero_areg)
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg;
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %1,%0\", xoperands);
else
output_asm_insn (\"mov %1,%0\", xoperands);
return \"\";
}
/* FALLTHROUGH */
case 4:
case 5:
case 6:
......@@ -238,20 +210,6 @@
case 2:
return \"clr %0\";
case 3:
if (zero_areg)
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg;
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %1,%0\", xoperands);
else
output_asm_insn (\"mov %1,%0\", xoperands);
return \"\";
}
/* FALLTHROUGH */
case 4:
case 5:
case 6:
......@@ -302,20 +260,6 @@
case 2:
return \"clr %0\";
case 3:
if (zero_areg)
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg;
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %1,%0\", xoperands);
else
output_asm_insn (\"mov %1,%0\", xoperands);
return \"\";
}
/* FALLTHROUGH */
case 4:
case 5:
return \"mov %1,%0\";
......@@ -357,17 +301,10 @@
return \"clr %L0\;clr %H0\";
case 3:
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg ? zero_areg : operands[1];
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %L1,%L0\;mov %L0,%H0\", xoperands);
else
output_asm_insn (\"mov %1,%L0\;mov %L0,%H0\", xoperands);
return \"\";
}
if (rtx_equal_p (operands[0], operands[1]))
return \"sub %L1,%L0\;mov %L0,%H0\";
else
return \"mov %1,%L0\;mov %L0,%H0\";
case 4:
case 5:
case 6:
......@@ -435,19 +372,6 @@
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
output_asm_insn (\"clr %L0\", operands);
else if (zero_areg
&& (REGNO_REG_CLASS (REGNO (operands[0]))
== ADDRESS_REGS))
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg;
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %L0,%L0\", xoperands);
else
output_asm_insn (\"mov %1,%L0\", xoperands);
}
else
output_asm_insn (\"mov %L1,%L0\", operands);
}
......@@ -460,19 +384,6 @@
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
output_asm_insn (\"clr %H0\", operands);
else if (zero_areg
&& (REGNO_REG_CLASS (REGNO (operands[0]))
== ADDRESS_REGS))
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg;
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %H0,%H0\", xoperands);
else
output_asm_insn (\"mov %1,%H0\", xoperands);
}
else
output_asm_insn (\"mov %H1,%H0\", operands);
}
......@@ -522,17 +433,10 @@
return \"clr %L0\;clr %H0\";
case 3:
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg ? zero_areg : operands[1];
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %L1,%L0\;mov %L0,%H0\", xoperands);
else
output_asm_insn (\"mov %1,%L0\;mov %L0,%H0\", xoperands);
return \"\";
}
if (rtx_equal_p (operands[0], operands[1]))
return \"sub %L1,%L0\;mov %L0,%H0\";
else
return \"mov %1,%L0\;mov %L0,%H0\";
case 4:
case 5:
case 6:
......@@ -600,19 +504,6 @@
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
output_asm_insn (\"clr %L0\", operands);
else if (zero_areg
&& (REGNO_REG_CLASS (REGNO (operands[0]))
== ADDRESS_REGS))
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg;
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %L0,%L0\", xoperands);
else
output_asm_insn (\"mov %1,%L0\", xoperands);
}
else
output_asm_insn (\"mov %L1,%L0\", operands);
}
......@@ -625,19 +516,6 @@
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
output_asm_insn (\"clr %H0\", operands);
else if (zero_areg
&& (REGNO_REG_CLASS (REGNO (operands[0]))
== ADDRESS_REGS))
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = zero_areg;
if (rtx_equal_p (xoperands[0], xoperands[1]))
output_asm_insn (\"sub %H0,%H0\", xoperands);
else
output_asm_insn (\"mov %1,%H0\", xoperands);
}
else
output_asm_insn (\"mov %H1,%H0\", operands);
}
......@@ -821,10 +699,7 @@
""
"*
{
if (zero_dreg)
output_asm_insn (\"mov %0,mdr\", &zero_dreg);
else
output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
if (find_reg_note (insn, REG_UNUSED, operands[3]))
return \"divu %2,%0\";
......
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