Skip to content

R
riscv-gcc-1
Commit 6e5b5de8 by Andreas Krebbel Committed by Andreas Krebbel
Options

S/390 Add vector scalar instruction support. 

With this patch GCC makes use of the vector instruction which are
available in single element mode.  By using these instructions scalar
double operations can use 32 registers.

gcc/
	* config/s390/s390-modes.def: Add new modes CCVEQ, CCVFH, and
	CCVFHE.
	* config/s390/s390.c (s390_match_ccmode_set): Handle new modes.
	(s390_select_ccmode): Likewise.
	(s390_canonicalize_comparison): Swap operands if necessary.
	(s390_expand_vec_compare_scalar): Expand DFmode compare using
	single element vector instructions.
	(s390_emit_compare): Call s390_expand_vec_compare_scalar.
	(s390_branch_condition_mask): Generate CC masks for the new modes.
	* config/s390/s390.md (v0, vf, vd): New mode attributes.
	(VFCMP, asm_fcmp, insn_cmp): New mode iterator and attributes.
	(*vec_cmp<insn_cmp>df_cconly, *fixuns_truncdfdi2_z13)
	(*fix_trunc<BFP:mode><GPR:mode>2_bfp, *floatunsdidf2_z13)
	(*floatuns<GPR:mode><FP:mode>2, *extendsfdf2_z13)
	(*extend<DSF:mode><BFP:mode>2): New insn definition.
	(fix_trunc<BFP:mode><GPR:mode>2_bfp, loatuns<GPR:mode><FP:mode>2)
	(extend<DSF:mode><BFP:mode>2): Turn into expander.
	(floatdi<mode>2, truncdfsf2, add<mode>3, sub<mode>3, mul<mode>3)
	(div<mode>3, *neg<mode>2, *abs<mode>2, *negabs<mode>2)
	(sqrt<mode>2): Add vector instruction.

gcc/testsuite/
	* gcc.target/s390/vector/vec-scalar-cmp-1.c: New test.

From-SVN: r223397
parent 91b019a3
Showing with 213 additions and 3 deletions
gcc/ChangeLog
2015-05-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390-modes.def: Add new modes CCVEQ, CCVFH, and
CCVFHE.
* config/s390/s390.c (s390_match_ccmode_set): Handle new modes.
(s390_select_ccmode): Likewise.
(s390_canonicalize_comparison): Swap operands if necessary.
(s390_expand_vec_compare_scalar): Expand DFmode compare using
single element vector instructions.
(s390_emit_compare): Call s390_expand_vec_compare_scalar.
(s390_branch_condition_mask): Generate CC masks for the new modes.
* config/s390/s390.md (v0, vf, vd): New mode attributes.
(VFCMP, asm_fcmp, insn_cmp): New mode iterator and attributes.
(*vec_cmp<insn_cmp>df_cconly, *fixuns_truncdfdi2_z13)
(*fix_trunc<BFP:mode><GPR:mode>2_bfp, *floatunsdidf2_z13)
(*floatuns<GPR:mode><FP:mode>2, *extendsfdf2_z13)
(*extend<DSF:mode><BFP:mode>2): New insn definition.
(fix_trunc<BFP:mode><GPR:mode>2_bfp, loatuns<GPR:mode><FP:mode>2)
(extend<DSF:mode><BFP:mode>2): Turn into expander.
(floatdi<mode>2, truncdfsf2, add<mode>3, sub<mode>3, mul<mode>3)
(div<mode>3, *neg<mode>2, *abs<mode>2, *negabs<mode>2)
(sqrt<mode>2): Add vector instruction.
2015-05-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/constraints.md (j00, jm1, jxx, jyy, v): New
constraints.
* config/s390/predicates.md (const0_operand, constm1_operand)
......
gcc/config/s390/s390-modes.def
......@@ -84,7 +84,12 @@ Requested mode -> Destination CC register mode
CCS, CCU, CCT, CCSR, CCUR -> CCZ
CCA -> CCAP, CCAN
Vector comparison modes
CCVEQ EQ - - NE (VCEQ)
CCVFH GT - - UNLE (VFCH)
CCVFHE GE - - UNLT (VFCHE)
*** Comments ***
CCAP, CCAN
......@@ -182,6 +187,11 @@ CC_MODE (CCT2);
CC_MODE (CCT3);
CC_MODE (CCRAW);
CC_MODE (CCVEQ);
CC_MODE (CCVFH);
CC_MODE (CCVFHE);
/* Vector modes. */
VECTOR_MODES (INT, 2); /* V2QI */
......
gcc/config/s390/s390.c
......@@ -681,6 +681,9 @@ s390_match_ccmode_set (rtx set, machine_mode req_mode)
case CCT1mode:
case CCT2mode:
case CCT3mode:
case CCVEQmode:
case CCVFHmode:
case CCVFHEmode:
if (req_mode != set_mode)
return 0;
break;
......@@ -781,6 +784,29 @@ s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
machine_mode
s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
{
if (TARGET_VX
&& register_operand (op0, DFmode)
&& register_operand (op1, DFmode))
{
/* LT, LE, UNGT, UNGE require swapping OP0 and OP1. Either
s390_emit_compare or s390_canonicalize_comparison will take
care of it. */
switch (code)
{
case EQ:
case NE:
return CCVEQmode;
case GT:
case UNLE:
return CCVFHmode;
case GE:
case UNLT:
return CCVFHEmode;
default:
;
}
}
switch (code)
{
case EQ:
......@@ -1058,8 +1084,73 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
rtx tem = *op0; *op0 = *op1; *op1 = tem;
*code = (int)swap_condition ((enum rtx_code)*code);
}
/* Using the scalar variants of vector instructions for 64 bit FP
comparisons might require swapping the operands. */
if (TARGET_VX
&& register_operand (*op0, DFmode)
&& register_operand (*op1, DFmode)
&& (*code == LT || *code == LE || *code == UNGT || *code == UNGE))
{
rtx tmp;
switch (*code)
{
case LT: *code = GT; break;
case LE: *code = GE; break;
case UNGT: *code = UNLE; break;
case UNGE: *code = UNLT; break;
default: ;
}
tmp = *op0; *op0 = *op1; *op1 = tmp;
}
}
/* Helper function for s390_emit_compare. If possible emit a 64 bit
FP compare using the single element variant of vector instructions.
Replace CODE with the comparison code to be used in the CC reg
compare and return the condition code register RTX in CC. */
static bool
s390_expand_vec_compare_scalar (enum rtx_code *code, rtx cmp1, rtx cmp2,
rtx *cc)
{
machine_mode cmp_mode;
bool swap_p = false;
switch (*code)
{
case EQ: cmp_mode = CCVEQmode; break;
case NE: cmp_mode = CCVEQmode; break;
case GT: cmp_mode = CCVFHmode; break;
case GE: cmp_mode = CCVFHEmode; break;
case UNLE: cmp_mode = CCVFHmode; break;
case UNLT: cmp_mode = CCVFHEmode; break;
case LT: cmp_mode = CCVFHmode; *code = GT; swap_p = true; break;
case LE: cmp_mode = CCVFHEmode; *code = GE; swap_p = true; break;
case UNGE: cmp_mode = CCVFHmode; *code = UNLE; swap_p = true; break;
case UNGT: cmp_mode = CCVFHEmode; *code = UNLT; swap_p = true; break;
default: return false;
}
if (swap_p)
{
rtx tmp = cmp2;
cmp2 = cmp1;
cmp1 = tmp;
}
*cc = gen_rtx_REG (cmp_mode, CC_REGNUM);
emit_insn (gen_rtx_PARALLEL (VOIDmode,
gen_rtvec (2,
gen_rtx_SET (*cc,
gen_rtx_COMPARE (cmp_mode, cmp1,
cmp2)),
gen_rtx_CLOBBER (VOIDmode,
gen_rtx_SCRATCH (V2DImode)))));
return true;
}
/* Emit a compare instruction suitable to implement the comparison
OP0 CODE OP1. Return the correct condition RTL to be placed in
the IF_THEN_ELSE of the conditional branch testing the result. */
......@@ -1070,10 +1161,18 @@ s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
machine_mode mode = s390_select_ccmode (code, op0, op1);
rtx cc;
/* Do not output a redundant compare instruction if a compare_and_swap
pattern already computed the result and the machine modes are compatible. */
if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
if (TARGET_VX
&& register_operand (op0, DFmode)
&& register_operand (op1, DFmode)
&& s390_expand_vec_compare_scalar (&code, op0, op1, &cc))
{
/* Work has been done by s390_expand_vec_compare_scalar already. */
}
else if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
{
/* Do not output a redundant compare instruction if a
compare_and_swap pattern already computed the result and the
machine modes are compatible. */
gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
== GET_MODE (op0));
cc = op0;
......@@ -1308,6 +1407,31 @@ s390_branch_condition_mask (rtx code)
}
break;
/* Vector comparison modes. */
case CCVEQmode:
switch (GET_CODE (code))
{
case EQ: return CC0;
case NE: return CC3;
default: return -1;
}
/* FP vector compare modes. */
case CCVFHmode:
switch (GET_CODE (code))
{
case GT: return CC0;
case UNLE: return CC3;
default: return -1;
}
case CCVFHEmode:
switch (GET_CODE (code))
{
case GE: return CC0;
case UNLT: return CC3;
default: return -1;
}
case CCRAWmode:
switch (GET_CODE (code))
{
......
gcc/testsuite/ChangeLog
2015-05-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/vector/vec-scalar-cmp-1.c: New test.
2015-05-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/s390.exp
(check_effective_target_vector): New check.
* gcc.target/s390/vector/vec-abi-1.c: New test.
......
gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c 0 → 100644
/* Check that we use the scalar variants of vector compares. */
/* { dg-do compile { target { s390*-*-* } } } */
/* { dg-options "-O3 -mzarch -march=z13" } */
/* { dg-final { scan-assembler-times "wfcedbs\t%v\[0-9\]*,%v0,%v2" 2 } } */
/* { dg-final { scan-assembler-times "wfchdbs\t%v\[0-9\]*,%v0,%v2" 1 } } */
/* { dg-final { scan-assembler-times "wfchedbs\t%v\[0-9\]*,%v2,%v0" 1 } } */
/* { dg-final { scan-assembler-times "wfchdbs\t%v\[0-9\]*,%v2,%v0" 1 } } */
/* { dg-final { scan-assembler-times "wfchedbs\t%v\[0-9\]*,%v2,%v0" 1 } } */
/* { dg-final { scan-assembler-times "locrne" 5 } } */
/* { dg-final { scan-assembler-times "locrno" 1 } } */
int
eq (double a, double b)
{
return a == b;
}
int
ne (double a, double b)
{
return a != b;
}
int
gt (double a, double b)
{
return a > b;
}
int
ge (double a, double b)
{
return a >= b;
}
int
lt (double a, double b)
{
return a < b;
}
int
le (double a, double b)
{
return a <= b;
}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment