Skip to content

R
riscv-gcc-1
Commit 6dd3234e by Kirill Yukhin Committed by H.J. Lu
Options

Fix operands order in BMI2 patterns. 

gcc/

2011-10-20  Kirill Yukhin  <kirill.yukhin@intel.com>

	PR target/50766
	* config/i386/i386.md (bmi_bextr_<mode>): Update register/
	memory operand order.
	(bmi2_bzhi_<mode>3): Ditto.
	(bmi2_pdep_<mode>3): Ditto.
	(bmi2_pext_<mode>3): Ditto.

gcc/testsuite/

2011-10-20  Kirill Yukhin  <kirill.yukhin@intel.com>

	PR target/50766
	* gcc.target/i386/pr50766.c: New test.

From-SVN: r180271
parent 5a3c0068
Showing with 39 additions and 8 deletions
gcc/ChangeLog
2011-10-20 Kirill Yukhin <kirill.yukhin@intel.com>
PR target/50766
* config/i386/i386.md (bmi_bextr_<mode>): Update register/
memory operand order.
(bmi2_bzhi_<mode>3): Ditto.
(bmi2_pdep_<mode>3): Ditto.
(bmi2_pext_<mode>3): Ditto.
2011-10-20 Richard Henderson <rth@redhat.com>
* target.def (vec_perm_const_ok): Rename from builtin_vec_perm_ok.
gcc/config/i386/i386.md
......@@ -12099,8 +12099,8 @@
(define_insn "bmi_bextr_<mode>"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
(match_operand:SWI48 2 "register_operand" "r")]
(unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
(match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_BEXTR))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI"
......@@ -12149,9 +12149,9 @@
;; BMI2 instructions.
(define_insn "bmi2_bzhi_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(and:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
(and:SWI48 (match_operand:SWI48 1 "register_operand" "r")
(lshiftrt:SWI48 (const_int -1)
(match_operand:SWI48 2 "register_operand" "r"))))
(match_operand:SWI48 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2"
"bzhi\t{%2, %1, %0|%0, %1, %2}"
......@@ -12161,8 +12161,8 @@
(define_insn "bmi2_pdep_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
(match_operand:SWI48 2 "register_operand" "r")]
(unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
(match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_PDEP))]
"TARGET_BMI2"
"pdep\t{%2, %1, %0|%0, %1, %2}"
......@@ -12172,8 +12172,8 @@
(define_insn "bmi2_pext_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
(match_operand:SWI48 2 "register_operand" "r")]
(unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
(match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_PEXT))]
"TARGET_BMI2"
"pext\t{%2, %1, %0|%0, %1, %2}"
......
gcc/testsuite/ChangeLog
2011-10-20 Kirill Yukhin <kirill.yukhin@intel.com>
PR target/50766
* gcc.target/i386/pr50766.c: New test.
2011-10-20 Jason Merrill <jason@redhat.com>
PR c++/41449
......
gcc/testsuite/gcc.target/i386/pr50766.c 0 → 100644
/* PR target/50766 */
/* { dg-do assemble } */
/* { dg-options "-mbmi2" } */
/* { dg-require-effective-target bmi2 } */
#include <x86intrin.h>
unsigned z;
void
foo ()
{
unsigned x = 0x23593464;
unsigned y = 0xF9494302;
z = _pext_u32(x, y);
}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment