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Commit 6d7d9f0e by Michael Meissner Committed by Michael Meissner
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re PR target/65849 (Add missing tuning knobs to #pragma target/attribute target support) 

[gcc]
2015-04-24  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/65849
	* config/rs6000/rs6000.opt (-mvsx-align-128): Make options that
	save to independent variables use the Save attribute.  This will
	allow these options to be modified with the #pragma/attribute
	target support.
	(-mallow-movmisalign): Likewise.
	(-mallow-df-permute): Likewise.
	(-msched-groups): Likewise.
	(-malways-hint): Likewise.
	(-malign-branch-targets): Likewise.
	(-mvectorize-builtins): Likewise.
	(-msave-toc-indirect): Likewise.

	* config/rs6000/rs6000.c (rs6000_opt_masks): Add more options that
	can be set via the #pragma/attribute target support.
	(rs6000_opt_vars): Likewise.
	(rs6000_inner_target_options): If VSX was set, also set
	-mno-avoid-indexed-addresses.

[gcc/testsuite]
2015-04-24  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/65849
	* gcc.target/powerpc/pr65849-1.c: New test to verify being able to
	set new options.
	* gcc.target/powerpc/pr65849-2.c: Likewise.

From-SVN: r222417
parent 728dc153
Showing with 85 additions and 13 deletions
gcc/ChangeLog
2015-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/65849
* config/rs6000/rs6000.opt (-mvsx-align-128): Make options that
save to independent variables use the Save attribute. This will
allow these options to be modified with the #pragma/attribute
target support.
(-mallow-movmisalign): Likewise.
(-mallow-df-permute): Likewise.
(-msched-groups): Likewise.
(-malways-hint): Likewise.
(-malign-branch-targets): Likewise.
(-mvectorize-builtins): Likewise.
(-msave-toc-indirect): Likewise.
* config/rs6000/rs6000.c (rs6000_opt_masks): Add more options that
can be set via the #pragma/attribute target support.
(rs6000_opt_vars): Likewise.
(rs6000_inner_target_options): If VSX was set, also set
-mno-avoid-indexed-addresses.
2015-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 2015-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/iterators.md (shiftable_ops): Rename to... * config/arm/iterators.md (shiftable_ops): Rename to...
......
gcc/config/rs6000/rs6000.c
...@@ -32219,10 +32219,11 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = ...@@ -32219,10 +32219,11 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true }, { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
{ "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true }, { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
{ "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
{ "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
{ "string", OPTION_MASK_STRING, false, true }, { "string", OPTION_MASK_STRING, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true }, { "update", OPTION_MASK_NO_UPDATE, true , true },
{ "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, false }, { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, true },
{ "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, false }, { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, true },
{ "vsx", OPTION_MASK_VSX, false, true }, { "vsx", OPTION_MASK_VSX, false, true },
{ "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true }, { "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
#ifdef OPTION_MASK_64BIT #ifdef OPTION_MASK_64BIT
...@@ -32295,6 +32296,42 @@ static struct rs6000_opt_var const rs6000_opt_vars[] = ...@@ -32295,6 +32296,42 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
{ "longcall", { "longcall",
offsetof (struct gcc_options, x_rs6000_default_long_calls), offsetof (struct gcc_options, x_rs6000_default_long_calls),
offsetof (struct cl_target_option, x_rs6000_default_long_calls), }, offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
{ "optimize-swaps",
offsetof (struct gcc_options, x_rs6000_optimize_swaps),
offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
{ "allow-movmisalign",
offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
{ "allow-df-permute",
offsetof (struct gcc_options, x_TARGET_ALLOW_DF_PERMUTE),
offsetof (struct cl_target_option, x_TARGET_ALLOW_DF_PERMUTE), },
{ "sched-groups",
offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
{ "always-hint",
offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
{ "align-branch-targets",
offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
{ "vectorize-builtins",
offsetof (struct gcc_options, x_TARGET_VECTORIZE_BUILTINS),
offsetof (struct cl_target_option, x_TARGET_VECTORIZE_BUILTINS), },
{ "tls-markers",
offsetof (struct gcc_options, x_tls_markers),
offsetof (struct cl_target_option, x_tls_markers), },
{ "sched-prolog",
offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
{ "sched-epilog",
offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
{ "gen-cell-microcode",
offsetof (struct gcc_options, x_rs6000_gen_cell_microcode),
offsetof (struct cl_target_option, x_rs6000_gen_cell_microcode), },
{ "warn-cell-microcode",
offsetof (struct gcc_options, x_rs6000_warn_cell_microcode),
offsetof (struct cl_target_option, x_rs6000_warn_cell_microcode), },
}; };
/* Inner function to handle attribute((target("..."))) and #pragma GCC target /* Inner function to handle attribute((target("..."))) and #pragma GCC target
...@@ -32368,9 +32405,15 @@ rs6000_inner_target_options (tree args, bool attr_p) ...@@ -32368,9 +32405,15 @@ rs6000_inner_target_options (tree args, bool attr_p)
rs6000_isa_flags_explicit |= mask; rs6000_isa_flags_explicit |= mask;
/* VSX needs altivec, so -mvsx automagically sets /* VSX needs altivec, so -mvsx automagically sets
altivec. */ altivec and disables -mavoid-indexed-addresses. */
if (mask == OPTION_MASK_VSX && !invert) if (!invert)
mask |= OPTION_MASK_ALTIVEC; {
if (mask == OPTION_MASK_VSX)
{
mask |= OPTION_MASK_ALTIVEC;
TARGET_AVOID_XFORM = 0;
}
}
if (rs6000_opt_masks[i].invert) if (rs6000_opt_masks[i].invert)
invert = !invert; invert = !invert;
...@@ -32391,6 +32434,7 @@ rs6000_inner_target_options (tree args, bool attr_p) ...@@ -32391,6 +32434,7 @@ rs6000_inner_target_options (tree args, bool attr_p)
size_t j = rs6000_opt_vars[i].global_offset; size_t j = rs6000_opt_vars[i].global_offset;
*((int *) ((char *)&global_options + j)) = !invert; *((int *) ((char *)&global_options + j)) = !invert;
error_p = false; error_p = false;
not_valid_p = false;
break; break;
} }
} }
gcc/config/rs6000/rs6000.opt
...@@ -204,11 +204,11 @@ mvsx-scalar-memory ...@@ -204,11 +204,11 @@ mvsx-scalar-memory
Target Undocumented Report Alias(mupper-regs-df) Target Undocumented Report Alias(mupper-regs-df)
mvsx-align-128 mvsx-align-128
Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
; If -mvsx, set alignment to 128 bits instead of 32/64 ; If -mvsx, set alignment to 128 bits instead of 32/64
mallow-movmisalign mallow-movmisalign
Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
; Allow/disallow the movmisalign in DF/DI vectors ; Allow/disallow the movmisalign in DF/DI vectors
mefficient-unaligned-vector mefficient-unaligned-vector
...@@ -216,23 +216,23 @@ Target Undocumented Report Var(TARGET_EFFICIENT_UNALIGNED_VSX) Init(-1) ...@@ -216,23 +216,23 @@ Target Undocumented Report Var(TARGET_EFFICIENT_UNALIGNED_VSX) Init(-1)
; Consider unaligned VSX accesses to be efficient/inefficient ; Consider unaligned VSX accesses to be efficient/inefficient
mallow-df-permute mallow-df-permute
Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save
; Allow/disallow permutation of DF/DI vectors ; Allow/disallow permutation of DF/DI vectors
msched-groups msched-groups
Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
; Explicitly set/unset whether rs6000_sched_groups is set ; Explicitly set/unset whether rs6000_sched_groups is set
malways-hint malways-hint
Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
; Explicitly set/unset whether rs6000_always_hint is set ; Explicitly set/unset whether rs6000_always_hint is set
malign-branch-targets malign-branch-targets
Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
; Explicitly set/unset whether rs6000_align_branch_targets is set ; Explicitly set/unset whether rs6000_align_branch_targets is set
mvectorize-builtins mvectorize-builtins
Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save
; Explicitly control whether we vectorize the builtins or not. ; Explicitly control whether we vectorize the builtins or not.
mno-update mno-update
...@@ -542,7 +542,7 @@ Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save ...@@ -542,7 +542,7 @@ Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
Use/do not use r11 to hold the static link in calls to functions via pointers. Use/do not use r11 to hold the static link in calls to functions via pointers.
msave-toc-indirect msave-toc-indirect
Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
Control whether we save the TOC in the prologue for indirect calls or generate the save inline Control whether we save the TOC in the prologue for indirect calls or generate the save inline
mvsx-timode mvsx-timode
......
gcc/testsuite/ChangeLog
2015-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/65849
* gcc.target/powerpc/pr65849-1.c: New test to verify being able to
set new options.
* gcc.target/powerpc/pr65849-2.c: Likewise.
2015-04-24 Tom de Vries <tom@codesourcery.com> 2015-04-24 Tom de Vries <tom@codesourcery.com>
PR tree-optimization/65802 PR tree-optimization/65802
......
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