Commit 6d7870d1 by James E Wilson Committed by Jim Wilson

Bug 14927

Bug 14927
* config/ia64/ia64.md (movxf): New local op0.  Handle case where
operands[0] is a SUBREG.  Handle case where operands[1] is a GR reg.

From-SVN: r81211
parent cf90fd1b
2004-04-26 James E Wilson <wilson@specifixinc.com>
Bug 14927
* config/ia64/ia64.md (movxf): New local op0. Handle case where
operands[0] is a SUBREG. Handle case where operands[1] is a GR reg.
2004-04-26 Zack Weinberg <zack@codesourcery.com> 2004-04-26 Zack Weinberg <zack@codesourcery.com>
* config/ia64/hpux.h: Predefine __STDCPP__ when compiling C++. * config/ia64/hpux.h: Predefine __STDCPP__ when compiling C++.
......
...@@ -677,12 +677,17 @@ ...@@ -677,12 +677,17 @@
(match_operand:XF 1 "general_operand" ""))] (match_operand:XF 1 "general_operand" ""))]
"" ""
{ {
rtx op0 = operands[0];
if (GET_CODE (op0) == SUBREG)
op0 = SUBREG_REG (op0);
/* We must support XFmode loads into general registers for stdarg/vararg /* We must support XFmode loads into general registers for stdarg/vararg
and unprototyped calls. We split them into DImode loads for convenience. and unprototyped calls. We split them into DImode loads for convenience.
We don't need XFmode stores from general regs, because a stdarg/vararg We don't need XFmode stores from general regs, because a stdarg/vararg
routine does a block store to memory of unnamed arguments. */ routine does a block store to memory of unnamed arguments. */
if (GET_CODE (operands[0]) == REG
&& GR_REGNO_P (REGNO (operands[0]))) if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
{ {
/* We're hoping to transform everything that deals with XFmode /* We're hoping to transform everything that deals with XFmode
quantities and GR registers early in the compiler. */ quantities and GR registers early in the compiler. */
...@@ -695,16 +700,23 @@ ...@@ -695,16 +700,23 @@
|| (GET_CODE (operands[1]) == REG || (GET_CODE (operands[1]) == REG
&& GR_REGNO_P (REGNO (operands[1])))) && GR_REGNO_P (REGNO (operands[1]))))
{ {
emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])), rtx op1 = operands[1];
SUBREG_REG (operands[1]));
if (GET_CODE (op1) == SUBREG)
op1 = SUBREG_REG (op1);
else
/* ??? Maybe we should make a SUBREG here? */
op1 = gen_rtx_REG (TImode, REGNO (op1));
emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
DONE; DONE;
} }
if (GET_CODE (operands[1]) == CONST_DOUBLE) if (GET_CODE (operands[1]) == CONST_DOUBLE)
{ {
emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])), emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
operand_subword (operands[1], 0, 0, XFmode)); operand_subword (operands[1], 0, 0, XFmode));
emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1), emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
operand_subword (operands[1], 1, 0, XFmode)); operand_subword (operands[1], 1, 0, XFmode));
DONE; DONE;
} }
...@@ -717,8 +729,8 @@ ...@@ -717,8 +729,8 @@
{ {
rtx out[2]; rtx out[2];
out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])); out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0));
out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1); out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0) + 1);
emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
......
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