Commit 6d6ab190 by David Edelsohn Committed by David Edelsohn

sysv4.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Define.

        * config/rs6000/sysv4.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Define.
        * config/rs6000/power4.md (power4-store,power4-vecstore): New
        insn reservations.
        (power4-fpstore): Compact.

From-SVN: r63167
parent 5b5142fb
2003-02-20 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/sysv4.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Define.
* config/rs6000/power4.md (power4-store,power4-vecstore): New
insn reservations.
(power4-fpstore): Compact.
2003-02-20 Kazu Hirata <kazu@cs.umass.edu> 2003-02-20 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.md (*iorsi3_w): New. * config/h8300/h8300.md (*iorsi3_w): New.
......
...@@ -127,9 +127,10 @@ ...@@ -127,9 +127,10 @@
"lsq_power4") "lsq_power4")
(define_insn_reservation "power4-store" 1 (define_insn_reservation "power4-store" 1
(and (eq_attr "type" "store,vecstore") (and (eq_attr "type" "store")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"lsq_power4") "((du1_power4|du4_power4),lsu1_power4,iu2_power4)\
|((du2_power4|du3_power4),lsu2_power4,iu1_power4)")
(define_insn_reservation "power4-store-update" 1 (define_insn_reservation "power4-store-update" 1
(and (eq_attr "type" "store_u") (and (eq_attr "type" "store_u")
...@@ -144,10 +145,8 @@ ...@@ -144,10 +145,8 @@
(define_insn_reservation "power4-fpstore" 1 (define_insn_reservation "power4-fpstore" 1
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"(du1_power4,fpu1_power4,lsu1_power4)\ "((du1_power4|du4_power4),lsu1_power4,fpu1_power4)\
|(du2_power4,fpu2_power4,lsu2_power4)\ |((du2_power4|du3_power4),lsu2_power4,fpu2_power4)")
|(du3_power4,fpu2_power4,lsu2_power4)\
|(du4_power4,fpu1_power4,lsu1_power4)")
(define_insn_reservation "power4-fpstore-update" 1 (define_insn_reservation "power4-fpstore-update" 1
(and (eq_attr "type" "fpstore_u") (and (eq_attr "type" "fpstore_u")
...@@ -163,6 +162,12 @@ ...@@ -163,6 +162,12 @@
"(du1_power4+du2_power4+du3_power4+du4_power4), "(du1_power4+du2_power4+du3_power4+du4_power4),
iu1_power4,fpu2_power4,(iu2_power4+lsu2_power4)") iu1_power4,fpu2_power4,(iu2_power4+lsu2_power4)")
(define_insn_reservation "power4-vecstore" 1
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power4"))
"((du1_power4|du4_power4),lsu1_power4,vec_power4)\
|((du2_power4|du3_power4),lsu2_power4,vec_power4)")
; Integer latency is 2 cycles ; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2 (define_insn_reservation "power4-integer" 2
......
...@@ -692,6 +692,20 @@ do { \ ...@@ -692,6 +692,20 @@ do { \
ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
} while (0) } while (0)
#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
/* To support -falign-* switches we need to use .p2align so
that alignment directives in code sections will be padded
with no-op instructions, rather than zeroes. */
#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
if ((LOG) != 0) \
{ \
if ((MAX_SKIP) == 0) \
fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
else \
fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
}
#endif
/* This is how to output code to push a register on the stack. /* This is how to output code to push a register on the stack.
It need not be very fast code. It need not be very fast code.
......
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