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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
6d53a79f
Commit
6d53a79f
authored
Jul 23, 2009
by
Richard Earnshaw
Committed by
Richard Earnshaw
Jul 23, 2009
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(split for ior/xor with shift and zero-extend): Cast op3 to
unsigned HWI. From-SVN: r150013
parent
fa89660f
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gcc/ChangeLog
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gcc/config/arm/arm.md
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gcc/ChangeLog
View file @
6d53a79f
2009-07-23 Richard Earnshaw <rearnsha@arm.com>
(split for ior/xor with shift and zero-extend): Cast op3 to
unsigned HWI.
2009-07-23 Uros Bizjak <ubizjak@gmail.com>
PR target/40832
...
...
gcc/config/arm/arm.md
View file @
6d53a79f
...
...
@@ -4219,7 +4219,7 @@
(match_operator 5 "subreg_lowpart_operator"
[
(match_operand:SI 4 "s_register_operand" "")
]
))))]
"TARGET_32BIT
&& (INTVAL (operands
[
3
]
)
&& (
(unsigned HOST_WIDE_INT)
INTVAL (operands
[
3
]
)
== (GET_MODE_MASK (GET_MODE (operands
[
5
]
))
& (GET_MODE_MASK (GET_MODE (operands
[
5
]
))
<< (INTVAL (operands
[
2
]
)))))"
...
...
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