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riscv-gcc-1
Commit 6d26dc3b by Kazu Hirata Committed by Kazu Hirata
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frv-protos.h: Add a prototype to frv_legitimate_memory_operand and frv_const_unspec_p. 

	* config/frv/frv-protos.h: Add a prototype to
	frv_legitimate_memory_operand and frv_const_unspec_p.
	(frv_unspec): Move from frv.c.
	* config/frv/frv.c (frv_unspec): Move to frv-protos.h.
	(frv_const_unspec_p, frv_legitimate_memory_operand_): Export.
	(ldd_address_operand, fdpic_fptr_operand, frv_load_operand,
	gpr_or_fpr_operand, gpr_or_int12_operand,
	gpr_fpr_or_int12_operand, fpr_or_int6_operand,
	gpr_or_int10_operand, gpr_or_int_operand, int12_operand,
	int6_operand, int5_operand, uint5_operand, uint4_operand,
	uint1_operand, int_2word_operand, uint16_operand,
	upper_int16_operand, integer_register_operand,
	gpr_no_subreg_operand, fpr_operand, even_reg_operand,
	odd_reg_operand, even_gpr_operand, odd_gpr_operand,
	quad_fpr_operand, even_fpr_operand, odd_fpr_operand,
	dbl_memory_one_insn_operand, dbl_memory_two_insn_operand,
	move_destination_operand, movcc_fp_destination_operand,
	frv_function_symbol_referenced_p, move_source_operand,
	condexec_dest_operand, condexec_source_operand,
	reg_or_0_operand, lr_operand, fdpic_operand, got12_operand,
	const_unspec_operand, gpr_or_memory_operand,
	gpr_or_memory_operand_with_scratch, fpr_or_memory_operand,
	icc_operand, fcc_operand, cc_operand, icr_operand,
	fcr_operand, cr_operand, call_operand, sibcall_operand,
	symbolic_operand, relational_operator,
	integer_relational_operator, float_relational_operator,
	ccr_eqne_operator, minmax_operator,
	condexec_si_binary_operator, condexec_si_media_operator,
	condexec_si_divide_operator, condexec_si_unary_operator,
	condexec_sf_conv_operator, condexec_sf_add_operator,
	condexec_memory_operand, intop_compare_operator, acc_operand,
	even_acc_operand, quad_acc_operand, accg_operand: Move to
	predicates.md.
	* config/frv/frv.h (PREDICATE_CODES): Remove.
	* config/frv/frv.md: Include predicates.md.
	* config/frv/predicates.md: New.

From-SVN: r97577
parent 2f84c996
Showing with 51 additions and 98 deletions
gcc/ChangeLog
......@@ -3,6 +3,43 @@
* config/frv/frv.h (PREDICATE_CODES): Add CONST to
gpr_or_int12_operand.
* config/frv/frv-protos.h: Add a prototype to
frv_legitimate_memory_operand and frv_const_unspec_p.
(frv_unspec): Move from frv.c.
* config/frv/frv.c (frv_unspec): Move to frv-protos.h.
(frv_const_unspec_p, frv_legitimate_memory_operand_): Export.
(ldd_address_operand, fdpic_fptr_operand, frv_load_operand,
gpr_or_fpr_operand, gpr_or_int12_operand,
gpr_fpr_or_int12_operand, fpr_or_int6_operand,
gpr_or_int10_operand, gpr_or_int_operand, int12_operand,
int6_operand, int5_operand, uint5_operand, uint4_operand,
uint1_operand, int_2word_operand, uint16_operand,
upper_int16_operand, integer_register_operand,
gpr_no_subreg_operand, fpr_operand, even_reg_operand,
odd_reg_operand, even_gpr_operand, odd_gpr_operand,
quad_fpr_operand, even_fpr_operand, odd_fpr_operand,
dbl_memory_one_insn_operand, dbl_memory_two_insn_operand,
move_destination_operand, movcc_fp_destination_operand,
frv_function_symbol_referenced_p, move_source_operand,
condexec_dest_operand, condexec_source_operand,
reg_or_0_operand, lr_operand, fdpic_operand, got12_operand,
const_unspec_operand, gpr_or_memory_operand,
gpr_or_memory_operand_with_scratch, fpr_or_memory_operand,
icc_operand, fcc_operand, cc_operand, icr_operand,
fcr_operand, cr_operand, call_operand, sibcall_operand,
symbolic_operand, relational_operator,
integer_relational_operator, float_relational_operator,
ccr_eqne_operator, minmax_operator,
condexec_si_binary_operator, condexec_si_media_operator,
condexec_si_divide_operator, condexec_si_unary_operator,
condexec_sf_conv_operator, condexec_sf_add_operator,
condexec_memory_operand, intop_compare_operator, acc_operand,
even_acc_operand, quad_acc_operand, accg_operand: Move to
predicates.md.
* config/frv/frv.h (PREDICATE_CODES): Remove.
* config/frv/frv.md: Include predicates.md.
* config/frv/predicates.md: New.
2004-04-04 Richard Sandiford <rsandifo@redhat.com>
PR target/19537
......
gcc/config/frv/frv-protos.h
......@@ -205,5 +205,18 @@ extern rtx frv_matching_accg_for_acc (rtx);
extern void frv_expand_fdpic_call (rtx *, bool, bool);
extern rtx frv_gen_GPsym2reg (rtx, rtx);
extern void frv_output_dwarf_dtprel (FILE *, int, rtx);
extern int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
/* Information about a relocation unspec. SYMBOL is the relocation symbol
(a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
is the constant addend. */
struct frv_unspec {
rtx symbol;
int reloc;
HOST_WIDE_INT offset;
};
extern bool frv_const_unspec_p (rtx, struct frv_unspec *);
#endif
gcc/config/frv/frv.h
......@@ -2758,104 +2758,6 @@ do { \
/* Miscellaneous Parameters. */
/* Define this if you have defined special-purpose predicates in the file
`MACHINE.c'. This macro is called within an initializer of an array of
structures. The first field in the structure is the name of a predicate and
the second field is an array of rtl codes. For each predicate, list all rtl
codes that can be in expressions matched by the predicate. The list should
have a trailing comma. Here is an example of two entries in the list for a
typical RISC machine:
#define PREDICATE_CODES \
{"gen_reg_rtx_operand", {SUBREG, REG}}, \
{"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
Defining this macro does not affect the generated code (however, incorrect
definitions that omit an rtl code that may be matched by the predicate can
cause the compiler to malfunction). Instead, it allows the table built by
`genrecog' to be more compact and efficient, thus speeding up the compiler.
The most important predicates to include in the list specified by this macro
are thoses used in the most insn patterns. */
#define PREDICATE_CODES \
{ "integer_register_operand", { REG, SUBREG }}, \
{ "frv_load_operand", { REG, SUBREG, MEM }}, \
{ "gpr_no_subreg_operand", { REG }}, \
{ "gpr_or_fpr_operand", { REG, SUBREG }}, \
{ "gpr_or_int12_operand", { REG, SUBREG, CONST_INT, CONST }}, \
{ "gpr_fpr_or_int12_operand", { REG, SUBREG, CONST_INT }}, \
{ "gpr_or_int10_operand", { REG, SUBREG, CONST_INT }}, \
{ "gpr_or_int_operand", { REG, SUBREG, CONST_INT }}, \
{ "move_source_operand", { REG, SUBREG, CONST_INT, MEM, \
CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF }}, \
{ "move_destination_operand", { REG, SUBREG, MEM }}, \
{ "movcc_fp_destination_operand", { REG, SUBREG, MEM }}, \
{ "condexec_source_operand", { REG, SUBREG, CONST_INT, MEM, \
CONST_DOUBLE }}, \
{ "condexec_dest_operand", { REG, SUBREG, MEM }}, \
{ "reg_or_0_operand", { REG, SUBREG, CONST_INT }}, \
{ "lr_operand", { REG }}, \
{ "gpr_or_memory_operand", { REG, SUBREG, MEM }}, \
{ "gpr_or_memory_operand_with_scratch", { REG, SUBREG, MEM }}, \
{ "fpr_or_memory_operand", { REG, SUBREG, MEM }}, \
{ "int12_operand", { CONST_INT }}, \
{ "int_2word_operand", { CONST_INT, CONST_DOUBLE, \
SYMBOL_REF, LABEL_REF, CONST }}, \
{ "fdpic_operand", { REG }}, \
{ "fdpic_fptr_operand", { REG }}, \
{ "ldd_address_operand", { REG, SUBREG, PLUS }}, \
{ "got12_operand", { CONST }}, \
{ "const_unspec_operand", { CONST }}, \
{ "icc_operand", { REG }}, \
{ "fcc_operand", { REG }}, \
{ "cc_operand", { REG }}, \
{ "icr_operand", { REG }}, \
{ "fcr_operand", { REG }}, \
{ "cr_operand", { REG }}, \
{ "fpr_operand", { REG, SUBREG }}, \
{ "even_reg_operand", { REG, SUBREG }}, \
{ "odd_reg_operand", { REG, SUBREG }}, \
{ "even_gpr_operand", { REG, SUBREG }}, \
{ "odd_gpr_operand", { REG, SUBREG }}, \
{ "quad_fpr_operand", { REG, SUBREG }}, \
{ "even_fpr_operand", { REG, SUBREG }}, \
{ "odd_fpr_operand", { REG, SUBREG }}, \
{ "dbl_memory_one_insn_operand", { MEM }}, \
{ "dbl_memory_two_insn_operand", { MEM }}, \
{ "call_operand", { REG, SUBREG, CONST_INT, \
CONST, SYMBOL_REF }}, \
{ "sibcall_operand", { REG, SUBREG, CONST_INT, \
CONST }}, \
{ "upper_int16_operand", { CONST_INT }}, \
{ "uint16_operand", { CONST_INT }}, \
{ "symbolic_operand", { SYMBOL_REF, CONST_INT }}, \
{ "relational_operator", { EQ, NE, LE, LT, GE, GT, \
LEU, LTU, GEU, GTU }}, \
{ "integer_relational_operator", { EQ, NE, LE, LT, GE, GT, \
LEU, LTU, GEU, GTU }}, \
{ "float_relational_operator", { EQ, NE, LE, LT, GE, GT }}, \
{ "ccr_eqne_operator", { EQ, NE }}, \
{ "minmax_operator", { SMIN, SMAX, UMIN, UMAX }}, \
{ "condexec_si_binary_operator", { PLUS, MINUS, AND, IOR, XOR, \
ASHIFT, ASHIFTRT, LSHIFTRT }}, \
{ "condexec_si_media_operator", { AND, IOR, XOR }}, \
{ "condexec_si_divide_operator", { DIV, UDIV }}, \
{ "condexec_si_unary_operator", { NOT, NEG }}, \
{ "condexec_sf_add_operator", { PLUS, MINUS }}, \
{ "condexec_sf_conv_operator", { ABS, NEG }}, \
{ "intop_compare_operator", { PLUS, MINUS, AND, IOR, XOR, \
ASHIFT, ASHIFTRT, LSHIFTRT }}, \
{ "fpr_or_int6_operand", { REG, SUBREG, CONST_INT }}, \
{ "int6_operand", { CONST_INT }}, \
{ "int5_operand", { CONST_INT }}, \
{ "uint5_operand", { CONST_INT }}, \
{ "uint4_operand", { CONST_INT }}, \
{ "uint1_operand", { CONST_INT }}, \
{ "acc_operand", { REG, SUBREG }}, \
{ "even_acc_operand", { REG, SUBREG }}, \
{ "quad_acc_operand", { REG, SUBREG }}, \
{ "accg_operand", { REG, SUBREG }},
/* An alias for a machine mode name. This is the machine mode that elements of
a jump-table should have. */
#define CASE_VECTOR_MODE SImode
......
gcc/config/frv/frv.md
......@@ -1504,6 +1504,7 @@
;; )
;;
(include "predicates.md")
;; ::::::::::::::::::::
;; ::
......
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