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riscv-gcc-1
Commit 6cf9eb27 by Kirill Yukhin Committed by Uros Bizjak
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i386.c: Remove traling spaces. 

       * config/i386/i386.c: Remove traling spaces.
       * config/i386/sse.md: Likewise.
       (*fma_fmadd_<mode>): Update.
       (*fma_fmsub_<mode>): Likewise.
       (*fma_fnmadd_<mode>): Likewise.
       (*fma_fnmsub_<mode>): Likewise.

From-SVN: r177588
parent d6257cf0
Showing with 42 additions and 33 deletions
gcc/ChangeLog
2011-08-09 Kirill Yukhin <kirill.yukhin@intel.com>
* config/i386/i386.c: Remove traling spaces.
* config/i386/sse.md: Likewise.
(*fma_fmadd_<mode>): Update.
(*fma_fmsub_<mode>): Likewise.
(*fma_fnmadd_<mode>): Likewise.
(*fma_fnmsub_<mode>): Likewise.
2011-08-09 Nick Clifton <nickc@redhat.com>
* config/rx/rx.md: Disable extender peepholes at -O3.
......
gcc/config/i386/i386.c
......@@ -120,7 +120,7 @@ check_avx256_stores (rtx dest, const_rtx set, void *data)
/* Helper function for move_or_delete_vzeroupper_1. Look for vzeroupper
in basic block BB. Delete it if upper 128bit AVX registers are
unused. If it isn't deleted, move it to just before a jump insn.
STATE is state of the upper 128bits of AVX registers at entry. */
static void
......@@ -2168,7 +2168,7 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
/* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
the auto-vectorizer. */
m_BDVER
m_BDVER
};
/* Feature tests against the various architecture variations. */
......@@ -3786,7 +3786,7 @@ ix86_option_override_internal (bool main_args_p)
target_flags |= MASK_PREFER_AVX128;
}
}
else
else
{
/* Disable vzeroupper pass if TARGET_AVX is disabled. */
target_flags &= ~MASK_VZEROUPPER;
......@@ -4707,8 +4707,8 @@ ix86_function_ok_for_sibcall (tree decl, tree exp)
optimize any indirect call, or a direct call to a global function,
as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
if (!TARGET_MACHO
&& !TARGET_64BIT
&& flag_pic
&& !TARGET_64BIT
&& flag_pic
&& (!decl || !targetm.binds_local_p (decl)))
return false;
......@@ -7514,7 +7514,7 @@ setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
before. */
ix86_varargs_gpr_size = 0;
ix86_varargs_fpr_size = 0;
for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
{
rtx reg, mem;
......@@ -8896,7 +8896,7 @@ choose_baseaddr_len (unsigned int regno, HOST_WIDE_INT offset)
return len;
}
/* Return an RTX that points to CFA_OFFSET within the stack frame.
The valid base registers are taken from CFUN->MACHINE->FS. */
......@@ -10361,7 +10361,7 @@ ix86_emit_restore_regs_using_mov (HOST_WIDE_INT cfa_offset,
{
rtx reg = gen_rtx_REG (Pmode, regno);
rtx insn, mem;
mem = choose_baseaddr (cfa_offset);
mem = gen_frame_mem (Pmode, mem);
insn = emit_move_insn (reg, mem);
......@@ -10709,7 +10709,7 @@ ix86_expand_epilogue (int style)
if (TARGET_VZEROUPPER
&& !TREE_THIS_VOLATILE (cfun->decl)
&& !cfun->machine->caller_return_avx256_p)
emit_insn (gen_avx_vzeroupper (GEN_INT (call_no_avx256)));
emit_insn (gen_avx_vzeroupper (GEN_INT (call_no_avx256)));
if (crtl->args.pops_args && crtl->args.size)
{
......@@ -11151,7 +11151,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
&& GET_MODE (addr) == DImode
&& GET_MODE (XEXP (addr, 0)) == SImode)
addr = XEXP (addr, 0);
if (REG_P (addr))
base = addr;
else if (GET_CODE (addr) == SUBREG)
......@@ -15084,7 +15084,7 @@ ix86_expand_move (enum machine_mode mode, rtx operands[])
}
}
if ((flag_pic || MACHOPIC_INDIRECT)
if ((flag_pic || MACHOPIC_INDIRECT)
&& symbolic_operand (op1, mode))
{
if (TARGET_MACHO && !TARGET_64BIT)
......@@ -15912,7 +15912,7 @@ ix86_split_idivmod (enum machine_mode mode, rtx operands[],
insn = emit_move_insn (operands[1], tmp1);
else
{
/* Need a new scratch register since the old one has result
/* Need a new scratch register since the old one has result
of 8bit divide. */
scratch = gen_reg_rtx (mode);
emit_move_insn (scratch, tmp1);
......@@ -22961,7 +22961,7 @@ ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
case AX_REG:
opcode = 0xb8; break;
case CX_REG:
opcode = 0xb9; break;
opcode = 0xb9; break;
default:
gcc_unreachable ();
}
......@@ -28291,7 +28291,7 @@ ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
/* This condition handles corner case where an expression involving
pointers gets vectorized. We're trying to use the address of a
stack slot as a vector initializer.
stack slot as a vector initializer.
(set (reg:V2DI 74 [ vect_cst_.2 ])
(vec_duplicate:V2DI (reg/f:DI 20 frame)))
......@@ -30008,7 +30008,7 @@ ix86_pad_returns (void)
/* Count the minimum number of instructions in BB. Return 4 if the
number of instructions >= 4. */
static int
static int
ix86_count_insn_bb (basic_block bb)
{
rtx insn;
......@@ -30037,10 +30037,10 @@ ix86_count_insn_bb (basic_block bb)
}
/* Count the minimum number of instructions in code path in BB.
/* Count the minimum number of instructions in code path in BB.
Return 4 if the number of instructions >= 4. */
static int
static int
ix86_count_insn (basic_block bb)
{
edge e;
......@@ -34950,7 +34950,7 @@ ix86_autovectorize_vector_sizes (void)
#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
#define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
#undef TARGET_SCHED_INIT_GLOBAL
#define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
gcc/config/i386/sse.md
......@@ -119,7 +119,7 @@
(V16QI "") (V8HI "") (V4SI "") (V2DI "")
(V8SF "256") (V4DF "256")
(V4SF "") (V2DF "")])
;; SSE instruction mode
(define_mode_attr sseinsnmode
[(V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")
......@@ -1717,7 +1717,7 @@
"TARGET_FMA"
"@
vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
vfmadd312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
......@@ -1732,7 +1732,7 @@
"TARGET_FMA"
"@
vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
vfmsub312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
......@@ -1747,7 +1747,7 @@
"TARGET_FMA"
"@
vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
vfnmadd312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfnmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfnmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
......@@ -1763,7 +1763,7 @@
"TARGET_FMA"
"@
vfnmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
vfnmsub312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfnmsub231<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfnmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
......@@ -2646,7 +2646,7 @@
ix86_build_const_vector (V2DFmode, 1, x));
operands[5] = gen_reg_rtx (V4SImode);
for (i = 6; i < 9; i++)
operands[i] = gen_reg_rtx (V2DFmode);
})
......@@ -2771,7 +2771,7 @@
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
emit_insn (gen_sse_movhlps (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
......@@ -2816,7 +2816,7 @@
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
emit_insn (gen_sse_movlhps (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
......@@ -3182,7 +3182,7 @@
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
emit_insn (gen_sse_loadhps (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
......@@ -3235,7 +3235,7 @@
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
emit_insn (gen_sse_loadlps (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
......@@ -4034,7 +4034,7 @@
[(V16QI "TARGET_SSE2")
(V8HI "TARGET_SSE2")
(V4SI "TARGET_SSE2")
(V2DI "TARGET_SSE2")
(V2DI "TARGET_SSE2")
(V8SF "TARGET_AVX") V4SF
(V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
......@@ -4236,7 +4236,7 @@
"TARGET_SSE2"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
emit_insn (gen_sse2_loadhpd (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
......@@ -4292,7 +4292,7 @@
"TARGET_SSE2"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
emit_insn (gen_sse2_loadlpd (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
......@@ -7260,7 +7260,7 @@
"@
phsubd\t{%2, %0|%0, %2}
vphsubd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
......@@ -10250,7 +10250,7 @@
rtx op1 = operands[1];
if (REG_P (op0))
op0 = gen_rtx_REG (<ssehalfvecmode>mode, REGNO (op0));
else
else
op1 = gen_rtx_REG (<MODE>mode, REGNO (op1));
emit_move_insn (op0, op1);
DONE;
......
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