Commit 6cd1d2e2 by Daniel Jacobowitz Committed by Nathan Froyd

rs6000.c (rs6000_dwarf_register_span): Fix debug output for other floating point modes.

	* config/rs6000/rs6000.c (rs6000_dwarf_register_span): Fix debug
	output for other floating point modes.

From-SVN: r146060
parent 68a607d8
2009-04-14 Daniel Jacobowitz <dan@codesourcery.com>
* config/rs6000/rs6000.c (rs6000_dwarf_register_span): Fix debug
output for other floating point modes.
2009-04-14 Diego Novillo <dnovillo@google.com> 2009-04-14 Diego Novillo <dnovillo@google.com>
Le-Chun Wu <lcwu@google.com> Le-Chun Wu <lcwu@google.com>
......
...@@ -22689,12 +22689,16 @@ rs6000_is_opaque_type (const_tree type) ...@@ -22689,12 +22689,16 @@ rs6000_is_opaque_type (const_tree type)
static rtx static rtx
rs6000_dwarf_register_span (rtx reg) rs6000_dwarf_register_span (rtx reg)
{ {
unsigned regno; rtx parts[8];
int i, words;
unsigned regno = REGNO (reg);
enum machine_mode mode = GET_MODE (reg);
if (TARGET_SPE if (TARGET_SPE
&& regno < 32
&& (SPE_VECTOR_MODE (GET_MODE (reg)) && (SPE_VECTOR_MODE (GET_MODE (reg))
|| (TARGET_E500_DOUBLE || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
&& (GET_MODE (reg) == DFmode || GET_MODE (reg) == DDmode)))) && mode != SFmode && mode != SDmode && mode != SCmode)))
; ;
else else
return NULL_RTX; return NULL_RTX;
...@@ -22704,15 +22708,23 @@ rs6000_dwarf_register_span (rtx reg) ...@@ -22704,15 +22708,23 @@ rs6000_dwarf_register_span (rtx reg)
/* The duality of the SPE register size wreaks all kinds of havoc. /* The duality of the SPE register size wreaks all kinds of havoc.
This is a way of distinguishing r0 in 32-bits from r0 in This is a way of distinguishing r0 in 32-bits from r0 in
64-bits. */ 64-bits. */
return words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
gen_rtx_PARALLEL (VOIDmode, gcc_assert (words <= 4);
BYTES_BIG_ENDIAN for (i = 0; i < words; i++, regno++)
? gen_rtvec (2, {
gen_rtx_REG (SImode, regno + 1200), if (BYTES_BIG_ENDIAN)
gen_rtx_REG (SImode, regno)) {
: gen_rtvec (2, parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
gen_rtx_REG (SImode, regno), parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
gen_rtx_REG (SImode, regno + 1200))); }
else
{
parts[2 * i] = gen_rtx_REG (SImode, regno);
parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
}
}
return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
} }
/* Fill in sizes for SPE register high parts in table used by unwinder. */ /* Fill in sizes for SPE register high parts in table used by unwinder. */
......
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