rs6000.md (anddi3_internal[23]): Prefer rldic?

        * rs6000.md (anddi3_internal[23]): Prefer rldic? over andis
        instruction.
        (cr logic): Really make operands sequential.

From-SVN: r37962

gcc/ChangeLog

+2000-12-02  David Edelsohn  <edelsohn@gnu.org>
+
+	* rs6000.md (anddi3_internal[23]): Prefer rldic? over andis
+	instruction.
+	(cr logic): Really make operands sequential.
+
 2000-12-02  Geoffrey Keating  <geoffk@redhat.com>
 
 	* c-common.c (combine_strings): When the ISO C standard specifies

gcc/config/rs6000/rs6000.md

@@ -6949,23 +6949,23 @@
    andis. %0,%1,%u2")
 
 (define_insn "*anddi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
 	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,")
-			    (match_operand:DI 2 "and64_operand" "r,K,J,S,r,K,J,S"))
+			    (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
 		    (const_int 0)))
    (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r"))
-   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
+   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
   "TARGET_POWERPC64"
   "@
    and. %3,%1,%2
+   rldic%B2. %3,%1,0,%S2
    andi. %3,%1,%b2
    andis. %3,%1,%u2
-   rldic%B2. %3,%1,0,%S2
    #
    #
    #
    #"
-  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,delayed_compare")
+  [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
    (set_attr "length" "4,4,4,4,8,8,8,8")])
 
 (define_split
@@ -6986,24 +6986,24 @@
   "")
 
 (define_insn "*anddi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
 	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
-			    (match_operand:DI 2 "and64_operand" "r,K,J,S,r,K,J,S"))
+			    (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
 		    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
 	(and:DI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
+   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
   "TARGET_POWERPC64"
   "@
    and. %0,%1,%2
+   rldic%B2. %0,%1,0,%S2
    andi. %0,%1,%b2
    andis. %0,%1,%u2
-   rldic%B2. %0,%1,0,%S2
    #
    #
    #
    #"
-  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,delayed_compare")
+  [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
    (set_attr "length" "4,4,4,4,8,8,8,8")])
 
 (define_split
@@ -12566,9 +12566,9 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
 
 (define_insn ""
   [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
-	(compare:CCEQ (match_operator:SI 2 
+	(compare:CCEQ (match_operator:SI 1
 				      "branch_positive_comparison_operator"
-				      [(match_operand 1
+				      [(match_operand 2
 						      "cc_reg_operand" "y")
 				       (const_int 0)])
 		      (const_int 0)))]