[ARM] Add Cortex-A17 support

	* config/arm/arm.md (generic_sched): Specify cortexa17 in 'no' list.
	Include cortex-a17.md.
	* config/arm/arm.c (arm_issue_rate): Specify 2 for cortexa17.
	* config/arm/arm-cores.def (cortex-a17): New entry.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Specify mcpu=cortex-a17.
	* config/arm/cortex-a17.md: New file.
	* config/arm/cortex-a17-neon.md: New file.
	* config/arm/driver-arm.c (arm_cpu_table): Add entry for cortex-a17.
	* config/arm/t-aprofile: Add cortex-a17 entries to MULTILIB_MATCHES.

From-SVN: r218145

gcc/ChangeLog

+2014-11-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/arm/arm.md (generic_sched): Specify cortexa17 in 'no' list.
+	Include cortex-a17.md.
+	* config/arm/arm.c (arm_issue_rate): Specify 2 for cortexa17.
+	* config/arm/arm-cores.def (cortex-a17): New entry.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Regenerate.
+	* config/arm/bpabi.h (BE8_LINK_SPEC): Specify mcpu=cortex-a17.
+	* config/arm/cortex-a17.md: New file.
+	* config/arm/cortex-a17-neon.md: New file.
+	* config/arm/driver-arm.c (arm_cpu_table): Add entry for cortex-a17.
+	* config/arm/t-aprofile: Add cortex-a17 entries to MULTILIB_MATCHES.
+
 2014-11-28  Richard Biener  <rguenther@suse.de>
 
 	PR middle-end/64084

gcc/config/arm/arm-cores.def

@@ -150,6 +150,7 @@ ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED, cortex_a8)
 ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,  FL_LDSCHED, cortex_a9)
 ARM_CORE("cortex-a12",	  	cortexa12, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
 ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
+ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
 ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,  FL_LDSCHED, cortex)
 ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,  FL_LDSCHED, cortex)
 ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,  FL_LDSCHED | FL_ARM_DIV, cortex)

gcc/config/arm/arm-tables.opt

@@ -271,6 +271,9 @@ EnumValue
 Enum(processor_type) String(cortex-a15) Value(cortexa15)
 
 EnumValue
+Enum(processor_type) String(cortex-a17) Value(cortexa17)
+
+EnumValue
 Enum(processor_type) String(cortex-r4) Value(cortexr4)
 
 EnumValue

gcc/config/arm/arm-tune.md

@@ -28,7 +28,7 @@
 	cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply,
 	genericv7a,cortexa5,cortexa7,
 	cortexa8,cortexa9,cortexa12,
-	cortexa15,cortexr4,cortexr4f,
+	cortexa15,cortexa17,cortexr4,cortexr4f,
 	cortexr5,cortexr7,cortexm7,
 	cortexm4,cortexm3,marvell_pj4,
 	cortexa15cortexa7,cortexa53,cortexa57,

gcc/config/arm/arm.c

@@ -27035,6 +27035,7 @@ arm_issue_rate (void)
     case cortexa8:
     case cortexa9:
     case cortexa12:
+    case cortexa17:
     case cortexa53:
     case fa726te:
     case marvell_pj4:

gcc/config/arm/arm.md

@@ -385,8 +385,8 @@
           (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,\
                                 arm926ejs,arm1020e,arm1026ejs,arm1136js,\
                                 arm1136jfs,cortexa5,cortexa7,cortexa8,\
-                                cortexa9,cortexa12,cortexa15,cortexa53,\
-                                cortexm4,cortexm7,marvell_pj4")
+                                cortexa9,cortexa12,cortexa15,cortexa17,\
+                                cortexa53,cortexm4,cortexm7,marvell_pj4")
 	       (eq_attr "tune_cortexr4" "yes"))
           (const_string "no")
           (const_string "yes"))))
@@ -417,6 +417,7 @@
 (include "cortex-a8.md")
 (include "cortex-a9.md")
 (include "cortex-a15.md")
+(include "cortex-a17.md")
 (include "cortex-a53.md")
 (include "cortex-r4.md")
 (include "cortex-r4f.md")

gcc/config/arm/bpabi.h

@@ -64,7 +64,7 @@
   " %{!mlittle-endian:%{march=armv7-a|mcpu=cortex-a5    \
    |mcpu=cortex-a7                                      \
    |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15       \
-   |mcpu=cortex-a12					\
+   |mcpu=cortex-a12|mcpu=cortex-a17			\
    |mcpu=cortex-a15.cortex-a7				\
    |mcpu=marvell-pj4					\
    |mcpu=cortex-a53					\
@@ -85,7 +85,7 @@
   " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5        \
    |mcpu=cortex-a7                                      \
    |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15       \
-   |mcpu=cortex-a12					\
+   |mcpu=cortex-a12|mcpu=cortex-a17			\
    |mcpu=cortex-a15.cortex-a7				\
    |mcpu=cortex-a53					\
    |mcpu=cortex-a57					\

gcc/config/arm/cortex-a17.md

+;; ARM Cortex-A17 pipeline description
+;; Copyright (C) 2014 Free Software Foundation, Inc.
+;;
+;; Contributed by ARM Ltd.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but
+;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+;; General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+(define_automaton "cortex_a17")
+
+(define_cpu_unit "ca17_ls0, ca17_ls1" "cortex_a17")
+(define_cpu_unit "ca17_alu0, ca17_alu1" "cortex_a17")
+(define_cpu_unit "ca17_mac" "cortex_a17")
+(define_cpu_unit "ca17_idiv" "cortex_a17")
+(define_cpu_unit "ca17_bx" "cortex_a17")
+
+(define_reservation "ca17_alu" "(ca17_alu0|ca17_alu1)")
+
+
+
+;; Simple Execution Unit:
+;;
+;; Simple ALU
+(define_insn_reservation "cortex_a17_alu" 1
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                        alu_sreg,alus_sreg,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr, mov_imm,mov_reg,\
+                        mvn_imm,mvn_reg,extend,\
+                        mrs,multiple,no_insn"))
+  "ca17_alu")
+
+(define_insn_reservation "cortex_a17_alu_shiftimm" 2
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "bfm,clz,rev,rbit, alu_shift_imm, alus_shift_imm,
+                        logic_shift_imm,alu_dsp_reg, logics_shift_imm,shift_imm,\
+                        shift_reg, mov_shift,mvn_shift"))
+  "ca17_alu")
+
+
+;; ALU ops with register controlled shift.
+(define_insn_reservation "cortex_a17_alu_shift_reg" 2
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                        logic_shift_reg,logics_shift_reg"))
+  "ca17_alu0")
+
+
+;; Multiply Execution Unit:
+
+;; 32-bit multiplies
+(define_insn_reservation "cortex_a17_mult32" 4
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "mul,muls,smmul,smmulr"))
+  "ca17_alu0+ca17_mac")
+
+(define_insn_reservation "cortex_a17_mac32" 4
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "mla,mlas,smmla"))
+  "ca17_alu0+ca17_mac,ca17_mac")
+
+(define_insn_reservation "cortex_a17_mac32_other" 3
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "smlad,smladx,smlsd,smlsdx,smuad,smuadx,smusd,smusdx"))
+  "ca17_alu0+ca17_mac,ca17_mac")
+
+;; 64-bit multiplies
+(define_insn_reservation "cortex_a17_mac64" 4
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "smlal,smlals,umaal,umlal,umlals"))
+  "ca17_alu0+ca17_mac,ca17_mac")
+
+(define_insn_reservation "cortex_a17_mac64_other" 3
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "smlald,smlalxy,smlsld"))
+  "ca17_alu0+ca17_mac,ca17_mac")
+
+(define_insn_reservation "cortex_a17_mult64" 4
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "smull,smulls,umull,umulls"))
+  "ca17_alu0+ca17_mac,ca17_mac")
+
+
+(define_bypass 2 "cortex_a17_mult*, cortex_a17_mac*"
+                 "cortex_a17_mult*, cortex_a17_mac*"
+                 "arm_mac_accumulator_is_result")
+
+;; Integer divide
+(define_insn_reservation "cortex_a17_udiv" 19
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "udiv"))
+  "ca17_alu1+ca17_idiv*10")
+
+(define_insn_reservation "cortex_a17_sdiv" 20
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "sdiv"))
+  "ca17_alu1+ca17_idiv*11")
+
+
+
+;; Branch execution Unit
+;;
+;; Branches take one issue slot.
+;; No latency as there is no result
+(define_insn_reservation "cortex_a17_branch" 0
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "branch"))
+  "ca17_bx")
+
+;; Load-store execution Unit
+;;
+;; Loads of up to two words.
+(define_insn_reservation "cortex_a17_load1" 4
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "load_byte,load1,load2"))
+  "ca17_ls0|ca17_ls1")
+
+;; Loads of three words.
+(define_insn_reservation "cortex_a17_load3" 4
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "load3"))
+  "ca17_ls0+ca17_ls1")
+
+;; Loads of four words.
+(define_insn_reservation "cortex_a17_load4" 4
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "load4"))
+  "ca17_ls0+ca17_ls1")
+
+;; Stores of up to two words.
+(define_insn_reservation "cortex_a17_store1" 0
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "store1,store2"))
+  "ca17_ls0|ca17_ls1")
+
+;; Stores of three words
+(define_insn_reservation "cortex_a17_store3" 0
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "store3"))
+  "ca17_ls0+ca17_ls1")
+
+;; Stores of four words.
+(define_insn_reservation "cortex_a17_store4" 0
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "store4"))
+  "ca17_ls0+ca17_ls1")
+
+(define_insn_reservation "cortex_a17_call" 0
+  (and (eq_attr "tune" "cortexa17")
+       (eq_attr "type" "call"))
+  "ca17_bx")
+
+
+(include "../arm/cortex-a17-neon.md")

gcc/config/arm/driver-arm.c

@@ -41,6 +41,7 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xc08", "armv7-a", "cortex-a8"},
     {"0xc09", "armv7-a", "cortex-a9"},
     {"0xc0d", "armv7ve", "cortex-a12"},
+    {"0xc0e", "armv7ve", "cortex-a17"},
     {"0xc0f", "armv7ve", "cortex-a15"},
     {"0xc14", "armv7-r", "cortex-r4"},
     {"0xc15", "armv7-r", "cortex-r5"},

gcc/config/arm/t-aprofile

@@ -83,6 +83,7 @@ MULTILIB_MATCHES       += march?armv7-a=mcpu?cortex-a9
 MULTILIB_MATCHES       += march?armv7-a=mcpu?cortex-a5
 MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a15
 MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a12
+MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a17
 MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a15.cortex-a7
 MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a53
 MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a57