Skip to content

R
riscv-gcc-1
Commit 6c174fc0 by Richard Henderson Committed by Richard Henderson
Options

c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset. 

* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST.  Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.

From-SVN: r17278
parent 8fbf199e
Showing with 205 additions and 19 deletions
gcc/ChangeLog
Fri Jan 2 04:34:14 1998 Richard Henderson <rth@cygnus.com>
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
Thu Jan 1 15:40:15 1998 Richard Henderson <rth@cygnus.com>
* configure.in: Put parenthesis around TARGET_CPU_DEFAULT's value.
......
gcc/c-decl.c
......@@ -3353,7 +3353,7 @@ init_decl_processing ()
builtin_function ("__builtin_memcmp", int_ftype_cptr_cptr_sizet,
BUILT_IN_MEMCMP, "memcmp");
builtin_function ("__builtin_memset", memset_ftype,
BUILT_IN_MEMSET, NULL_PTR);
BUILT_IN_MEMSET, "memset");
builtin_function ("__builtin_strcmp", int_ftype_string_string,
BUILT_IN_STRCMP, "strcmp");
builtin_function ("__builtin_strcpy", string_ftype_ptr_ptr,
......@@ -3450,8 +3450,6 @@ init_decl_processing ()
BUILT_IN_FMOD, NULL_PTR);
builtin_function ("__builtin_frem", double_ftype_double_double,
BUILT_IN_FREM, NULL_PTR);
builtin_function ("__builtin_memset", ptr_ftype_ptr_int_int,
BUILT_IN_MEMSET, NULL_PTR);
builtin_function ("__builtin_getexp", double_ftype_double, BUILT_IN_GETEXP,
NULL_PTR);
builtin_function ("__builtin_getman", double_ftype_double, BUILT_IN_GETMAN,
......
gcc/config/alpha/alpha.h
......@@ -384,18 +384,22 @@ extern void override_options ();
??? Kludge this and the next macro for the moment by not doing anything if
we don't optimize and also if we are writing ECOFF symbols to work around
a bug in DEC's assembler. */
/* Aligning past 2**3 wastes insn cache lines, and doesn't buy much
issue-wise on average anyway. */
#define ASM_OUTPUT_LOOP_ALIGN(FILE) \
if (optimize > 0 && write_symbols != SDB_DEBUG) \
ASM_OUTPUT_ALIGN (FILE, 5)
ASM_OUTPUT_ALIGN (FILE, 3)
/* This is how to align an instruction for optimal branching.
On Alpha we'll get better performance by aligning on a quadword
boundary. */
/* Aligning past 2**3 wastes insn cache lines, and doesn't buy much
issue-wise on average anyway. */
#define ASM_OUTPUT_ALIGN_CODE(FILE) \
if (optimize > 0 && write_symbols != SDB_DEBUG) \
ASM_OUTPUT_ALIGN ((FILE), 4)
ASM_OUTPUT_ALIGN ((FILE), 3)
/* No data type wants to be aligned rounder than this. */
#define BIGGEST_ALIGNMENT 64
......@@ -406,8 +410,12 @@ extern void override_options ();
/* Align all constants and variables to at least a word boundary so
we can pick up pieces of them faster. */
/* ??? Only if block-move stuff knows about different source/destination
alignment. */
#if 0
#define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
#define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
#endif
/* Set this non-zero if move instructions will actually fail to work
when given unaligned data.
......@@ -1509,6 +1517,12 @@ extern void alpha_init_expanders ();
#define MOVE_MAX 8
/* Controls how many units are moved by expr.c before resorting to movstr.
Without byte/word accesses, we want no more than one; with, several single
byte accesses are better. */
#define MOVE_RATIO (TARGET_BWX ? 7 : 2)
/* Largest number of bytes of an object that can be placed in a register.
On the Alpha we have plenty of registers, so use TImode. */
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
......
gcc/config/alpha/alpha.md
......@@ -1431,7 +1431,7 @@
"ext%M2l %r1,%s3,%0"
[(set_attr "type" "shift")])
(define_insn ""
(define_insn "extxl"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
(match_operand:DI 2 "mode_width_operand" "n")
......@@ -1441,7 +1441,7 @@
"ext%M2l %r1,%3,%0"
[(set_attr "type" "shift")])
(define_insn ""
(define_insn "extqh"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI
(match_operand:DI 1 "reg_or_0_operand" "rJ")
......@@ -1456,7 +1456,7 @@
"extqh %r1,%2,%0"
[(set_attr "type" "shift")])
(define_insn ""
(define_insn "extlh"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI
(and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
......@@ -1472,7 +1472,7 @@
"extlh %r1,%2,%0"
[(set_attr "type" "shift")])
(define_insn ""
(define_insn "extwh"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI
(and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
......@@ -1538,7 +1538,7 @@
"insll %1,%s2,%0"
[(set_attr "type" "shift")])
(define_insn ""
(define_insn "insbl"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
......@@ -1547,7 +1547,7 @@
"insbl %1,%2,%0"
[(set_attr "type" "shift")])
(define_insn ""
(define_insn "inswl"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
......@@ -1556,7 +1556,7 @@
"inswl %1,%2,%0"
[(set_attr "type" "shift")])
(define_insn ""
(define_insn "insll"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
......@@ -1565,10 +1565,30 @@
"insll %1,%2,%0"
[(set_attr "type" "shift")])
(define_insn "insql"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI (match_operand:DI 1 "register_operand" "r")
(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
(const_int 3))))]
""
"insql %1,%2,%0"
[(set_attr "type" "shift")])
;; We do not include the insXh insns because they are complex to express
;; and it does not appear that we would ever want to generate them.
;;
;; Since we need them for block moves, though, cop out and use unspec.
(define_insn ""
(define_insn "insxh"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "mode_width_operand" "n")
(match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
""
"ins%M2h %1,%3,%0"
[(set_attr "type" "shift")])
(define_insn "mskxl"
[(set (match_operand:DI 0 "register_operand" "=r")
(and:DI (not:DI (ashift:DI
(match_operand:DI 2 "mode_mask_operand" "n")
......@@ -1580,8 +1600,19 @@
"msk%U2l %r1,%3,%0"
[(set_attr "type" "shift")])
;; We do not include the mskXh insns because it does not appear we would ever
;; generate one.
;; We do not include the mskXh insns because it does not appear we would
;; ever generate one.
;;
;; Again, we do for block moves and we use unspec again.
(define_insn "mskxh"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "mode_width_operand" "n")
(match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
""
"msk%M2h %1,%3,%0"
[(set_attr "type" "shift")])
;; Floating-point operations. All the double-precision insns can extend
;; from single, so indicate that. The exception are the ones that simply
......@@ -4781,6 +4812,122 @@
DONE;
}")
;; Bit field extract patterns which use ext[wlq][lh]
(define_expand "extv"
[(set (match_operand:DI 0 "register_operand" "")
(sign_extract:DI (match_operand:QI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")
(match_operand:DI 3 "immediate_operand" "")))]
""
"
{
/* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
if (INTVAL (operands[3]) % 8 != 0
|| (INTVAL (operands[2]) != 16
&& INTVAL (operands[2]) != 32
&& INTVAL (operands[2]) != 64))
FAIL;
/* From mips.md: extract_bit_field doesn't verify that our source
matches the predicate, so we force it to be a MEM here. */
if (GET_CODE (operands[1]) != MEM)
FAIL;
alpha_expand_unaligned_load (operands[0], operands[1],
INTVAL (operands[2]) / 8,
INTVAL (operands[3]) / 8, 1);
DONE;
}")
(define_expand "extzv"
[(set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_operand:QI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")
(match_operand:DI 3 "immediate_operand" "")))]
""
"
{
/* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
if (INTVAL (operands[3]) % 8 != 0
|| (INTVAL (operands[2]) != 16
&& INTVAL (operands[2]) != 32
&& INTVAL (operands[2]) != 64))
FAIL;
/* From mips.md: extract_bit_field doesn't verify that our source
matches the predicate, so we force it to be a MEM here. */
if (GET_CODE (operands[1]) != MEM)
FAIL;
alpha_expand_unaligned_load (operands[0], operands[1],
INTVAL (operands[2]) / 8,
INTVAL (operands[3]) / 8, 0);
DONE;
}")
(define_expand "insv"
[(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
(match_operand:DI 1 "immediate_operand" "")
(match_operand:DI 2 "immediate_operand" ""))
(match_operand:DI 3 "register_operand" ""))]
""
"
{
/* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
if (INTVAL (operands[2]) % 8 != 0
|| (INTVAL (operands[1]) != 16
&& INTVAL (operands[1]) != 32
&& INTVAL (operands[1]) != 64))
FAIL;
/* From mips.md: store_bit_field doesn't verify that our source
matches the predicate, so we force it to be a MEM here. */
if (GET_CODE (operands[0]) != MEM)
FAIL;
alpha_expand_unaligned_store (operands[0], operands[3],
INTVAL (operands[1]) / 8,
INTVAL (operands[2]) / 8);
DONE;
}")
;; Block move/clear, see alpha.c for more details.
;; Argument 0 is the destination
;; Argument 1 is the source
;; Argument 2 is the length
;; Argument 3 is the alignment
(define_expand "movstrqi"
[(parallel [(set (match_operand:BLK 0 "general_operand" "")
(match_operand:BLK 1 "general_operand" ""))
(use (match_operand:DI 2 "immediate_operand" ""))
(use (match_operand:DI 3 "immediate_operand" ""))])]
""
"
{
if (alpha_expand_block_move (operands))
DONE;
else
FAIL;
}")
(define_expand "clrstrqi"
[(parallel [(set (match_operand:BLK 0 "general_operand" "")
(const_int 0))
(use (match_operand:DI 1 "immediate_operand" ""))
(use (match_operand:DI 2 "immediate_operand" ""))])]
""
"
{
if (alpha_expand_block_clear (operands))
DONE;
else
FAIL;
}")
;; Subroutine of stack space allocation. Perform a stack probe.
(define_expand "probe_stack"
[(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
......
gcc/expr.c
......@@ -9036,7 +9036,7 @@ expand_builtin (exp, target, subtarget, mode, ignore)
|| (TREE_CODE (TREE_TYPE (TREE_VALUE (TREE_CHAIN (arglist))))
!= INTEGER_TYPE)
|| TREE_CHAIN (TREE_CHAIN (arglist)) == 0
|| (INTEGER_CST
|| (INTEGER_TYPE
!= (TREE_CODE (TREE_TYPE
(TREE_VALUE
(TREE_CHAIN (TREE_CHAIN (arglist))))))))
......@@ -9061,11 +9061,16 @@ expand_builtin (exp, target, subtarget, mode, ignore)
if (expand_expr (val, NULL_RTX, VOIDmode, 0) != const0_rtx)
break;
/* If LEN does not expand to a constant, don't do this
operation in-line. */
len_rtx = expand_expr (len, NULL_RTX, VOIDmode, 0);
if (GET_CODE (len_rtx) != CONST_INT)
break;
dest_rtx = expand_expr (dest, NULL_RTX, ptr_mode, EXPAND_SUM);
dest_mem = gen_rtx (MEM, BLKmode,
memory_address (BLKmode, dest_rtx));
len_rtx = expand_expr (len, NULL_RTX, VOIDmode, 0);
/* Just check DST is writable and mark it as readable. */
if (flag_check_memory_usage)
emit_library_call (chkr_check_addr_libfunc, 1, VOIDmode, 3,
......@@ -9074,7 +9079,6 @@ expand_builtin (exp, target, subtarget, mode, ignore)
GEN_INT (MEMORY_USE_WO),
TYPE_MODE (integer_type_node));
/* There could be a void* cast on top of the object. */
while (TREE_CODE (dest) == NOP_EXPR)
dest = TREE_OPERAND (dest, 0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment