h8300.c (output_simode_bld): Handle H8/300 and H8/300[HS] separately.

	* config/h8300/h8300.c (output_simode_bld): Handle H8/300 and
	H8/300[HS] separately.
	* config/h8300/h8300.md: Remove the early clobber constraint
	from bit field patterns.

From-SVN: r49995

gcc/ChangeLog

 2002-02-23  Kazu Hirata  <kazu@hxi.com>
 
+	* config/h8300/h8300.c (output_simode_bld): Handle H8/300 and
+	H8/300[HS] separately.
+	* config/h8300/h8300.md: Remove the early clobber constraint
+	from bit field patterns.
+
+2002-02-23  Kazu Hirata  <kazu@hxi.com>
+
 	* config/h8300/h8300.md (mulqihi3): Tighten predicates to
 	register_operand.
 	(mulhisi3): Likewise.

gcc/config/h8300/h8300.c

@@ -3120,18 +3120,31 @@ output_simode_bld (bild, operands)
      int bild;
      rtx operands[];
 {
-  /* Clear the destination register.  */
-  if (TARGET_H8300H || TARGET_H8300S)
-    output_asm_insn ("sub.l\t%S0,%S0", operands);
-  else
-    output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
+  if (TARGET_H8300)
+    {
+      /* Clear the destination register.  */
+      output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
+
+      /* Now output the bit load or bit inverse load, and store it in
+	 the destination.  */
+      if (bild)
+	output_asm_insn ("bild\t%Z2,%Y1", operands);
+      else
+	output_asm_insn ("bld\t%Z2,%Y1", operands);
 
-  /* Now output the bit load or bit inverse load, and store it in
-     the destination.  */
-  if (bild)
-    output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
+      output_asm_insn ("bst\t#0,%w0", operands);
+    }
   else
-    output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
+    {
+      /* Output the bit load or bit inverse load.  */
+      if (bild)
+	output_asm_insn ("bild\t%Z2,%Y1", operands);
+      else
+	output_asm_insn ("bld\t%Z2,%Y1", operands);
+
+      /* Clear the destination register and perform the bit store.  */
+      output_asm_insn ("xor.l\t%S0,%S0\n\tbst\t#0,%w0", operands);
+    }
 
   /* All done.  */
   return "";

gcc/config/h8300/h8300.md

@@ -2031,7 +2031,7 @@
    (set_attr "length" "6")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
+  [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 			 (const_int 1)
 			 (match_operand 2 "const_int_operand" "n")))]
@@ -2059,7 +2059,7 @@
    (set_attr "length" "6")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
+  [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
 				 (match_operand 3 "const_int_operand" "n"))
 			 (const_int 1)