SH: resurect -mfmovd

From-SVN: r149803

gcc/ChangeLog

+2009-07-20  Christian Bruel  <christian.bruel@st.com>
+	
+	* config/sh/sh.opt (-mfmovd): Resurrect and document.
+	* doc/invoke.texi (-mfmovd): Likewise.
+	* config/sh/sh.h (TARGET_FMOVD, MASK_FMOVD): Remove default setting.
+	
 2009-07-20  Jan Hubicka  <jh@suse.cz>
 
 	* tree-ssa-dce.c (remove_dead_phis): Only look for abnormal PHIs
@@ -127,6 +133,7 @@
 	* c-omp.c (c_finish_omp_atomic): Set DECL_CONTEXT on the
 	temporary variable.
 
+>>>>>>> .r149802
 2009-07-17  Sandra Loosemore  <sandra@codesourcery.com>
 
 	* doc/service.texi (Service): Restore previously removed link,
@@ -146,6 +153,7 @@
 	* gimplify.c (gimplify_conversion): Don't change non-conversions into
 	VIEW_CONVERT_EXPR.
 
+>>>>>>> .r149747
 2009-07-16  Sandra Loosemore  <sandra@codesourcery.com>
 
 	* doc/extend.texi (Nested Functions): Replace broken link with

gcc/config/sh/sh.h

@@ -28,11 +28,6 @@ along with GCC; see the file COPYING3.  If not see
 #define TARGET_VERSION \
   fputs (" (Hitachi SH)", stderr);
 
-#ifndef TARGET_FMOVD
-#define TARGET_FMOVD 0
-#define MASK_FMOVD   0
-#endif
-
 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h.  We can't
    include it here, because bconfig.h is also included by gencodes.c .  */
 /* ??? No longer true.  */

gcc/config/sh/sh.opt

@@ -244,6 +244,10 @@ mdivsi3_libfunc=
 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
 Specify name for 32 bit signed division function
 
+mfmovd
+Target RejectNegative Mask(FMOVD)
+Enable the use of 64-bit floating point registers in fmov instructions.  See -mdalign if 64-bit alignment is required.
+
 mfixed-range=
 Target RejectNegative Joined Var(sh_fixed_range_str)
 Specify range of registers to make fixed
@@ -312,7 +316,7 @@ Follow Renesas (formerly Hitachi) / SuperH calling conventions
 
 mspace
 Target Report RejectNegative Mask(SMALLCODE)
-Deprecated. Use -Os instead
+Deprecated.  Use -Os instead
 
 multcost=
 Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)

gcc/doc/invoke.texi

@@ -800,7 +800,7 @@ See RS/6000 and PowerPC Options.
 -m5-32media  -m5-32media-nofpu @gol
 -m5-compact  -m5-compact-nofpu @gol
 -mb  -ml  -mdalign  -mrelax @gol
--mbigtable  -mhitachi -mrenesas -mno-renesas -mnomacsave @gol
+-mbigtable -mfmovd -mhitachi -mrenesas -mno-renesas -mnomacsave @gol
 -mieee  -mbitops  -misize  -minline-ic_invalidate -mpadstruct  -mspace @gol
 -mprefergot  -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
 -mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
@@ -15306,6 +15306,11 @@ Use 32-bit offsets in @code{switch} tables.  The default is to use
 @opindex mbitops
 Enable the use of bit manipulation instructions on SH2A.
 
+@item -mfmovd
+@opindex mfmovd
+Enable the use of the instruction @code{fmovd}.  Check @option{-mdalign} for
+alignment constraints.
+
 @item -mhitachi
 @opindex mhitachi
 Comply with the calling conventions defined by Renesas.

gcc/testsuite/ChangeLog

+2009-07-20  Christian Bruel  <christian.bruel@st.com>
+	
+	* gcc.target/sh/mfmovd.c: New test.
+	
 2009-07-19  Janne Blomqvist  <jb@gcc.gnu.org>
 	    Jerry DeLisle  <jvdelisle@gcc.gnu.org>
 
@@ -52,6 +56,7 @@
 	* gcc.target/powerpc/asm-es-1.c: New test.
 	* gcc.target/powerpc/asm-es-2.c: Likewise.
 
+>>>>>>> .r149802
 2009-07-17  Richard Guenther  <rguenther@suse.de>
 
 	PR c/40401
@@ -84,6 +89,7 @@
 	PR c++/40780
 	* g++.dg/template/ptrmem19.C: New test.
 
+>>>>>>> .r149747
 2009-07-17  Aldy Hernandez  <aldyh@redhat.com>
 	    Manuel López-Ibáñez  <manu@gcc.gnu.org>
 

gcc/testsuite/gcc.target/sh/mfmovd.c

+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-mfmovd" } */
+/* { dg-skip-if "No double precision FPU support" { "sh*-*-*" } "-m2a-nofpu -m2a-single-only -m4-nofpu -m4-single-only -m4a-nofpu -m4a-single-only" { "" } }  */
+/* { dg-final { scan-assembler "fmov.d"} }  */
+
+extern double g;
+
+void
+f (double d)
+{
+  g = d;
+}
+