Commit 6a24a83e by James Greenhalgh Committed by James Greenhalgh

[Patch AArch64] Fix types for some multiply instructions.

gcc/
	* config/aarch64/aarch64.md
	(*madd<mode>): Fix type attribute.
	(*maddsi_uxtw): Likewise.
	(*msub<mode>): Likewise.
	(*msubsi_uxtw): Likewise.
	(<su_optab>maddsidi4): Likewise.
	(<su_optab>msubsidi4): Likewise.

From-SVN: r202330
parent b86923f0
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com> 2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(*madd<mode>): Fix type attribute.
(*maddsi_uxtw): Likewise.
(*msub<mode>): Likewise.
(*msubsi_uxtw): Likewise.
(<su_optab>maddsidi4): Likewise.
(<su_optab>msubsidi4): Likewise.
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md: Split fdiv<sd> as fsqrt<sd>, fdiv<sd>. * config/arm/types.md: Split fdiv<sd> as fsqrt<sd>, fdiv<sd>.
* config/arm/arm.md (core_cycles): Remove fdiv. * config/arm/arm.md (core_cycles): Remove fdiv.
* config/arm/vfp.md: * config/arm/vfp.md:
......
...@@ -2281,7 +2281,7 @@ ...@@ -2281,7 +2281,7 @@
"" ""
"madd\\t%<w>0, %<w>1, %<w>2, %<w>3" "madd\\t%<w>0, %<w>1, %<w>2, %<w>3"
[(set_attr "v8type" "madd") [(set_attr "v8type" "madd")
(set_attr "type" "mul") (set_attr "type" "mla")
(set_attr "mode" "<MODE>")] (set_attr "mode" "<MODE>")]
) )
...@@ -2295,7 +2295,7 @@ ...@@ -2295,7 +2295,7 @@
"" ""
"madd\\t%w0, %w1, %w2, %w3" "madd\\t%w0, %w1, %w2, %w3"
[(set_attr "v8type" "madd") [(set_attr "v8type" "madd")
(set_attr "type" "mul") (set_attr "type" "mla")
(set_attr "mode" "SI")] (set_attr "mode" "SI")]
) )
...@@ -2308,7 +2308,7 @@ ...@@ -2308,7 +2308,7 @@
"" ""
"msub\\t%<w>0, %<w>1, %<w>2, %<w>3" "msub\\t%<w>0, %<w>1, %<w>2, %<w>3"
[(set_attr "v8type" "madd") [(set_attr "v8type" "madd")
(set_attr "type" "mul") (set_attr "type" "mla")
(set_attr "mode" "<MODE>")] (set_attr "mode" "<MODE>")]
) )
...@@ -2323,7 +2323,7 @@ ...@@ -2323,7 +2323,7 @@
"" ""
"msub\\t%w0, %w1, %w2, %w3" "msub\\t%w0, %w1, %w2, %w3"
[(set_attr "v8type" "madd") [(set_attr "v8type" "madd")
(set_attr "type" "mul") (set_attr "type" "mla")
(set_attr "mode" "SI")] (set_attr "mode" "SI")]
) )
...@@ -2373,7 +2373,7 @@ ...@@ -2373,7 +2373,7 @@
"" ""
"<su>maddl\\t%0, %w1, %w2, %3" "<su>maddl\\t%0, %w1, %w2, %3"
[(set_attr "v8type" "maddl") [(set_attr "v8type" "maddl")
(set_attr "type" "mul") (set_attr "type" "<su>mlal")
(set_attr "mode" "DI")] (set_attr "mode" "DI")]
) )
...@@ -2387,7 +2387,7 @@ ...@@ -2387,7 +2387,7 @@
"" ""
"<su>msubl\\t%0, %w1, %w2, %3" "<su>msubl\\t%0, %w1, %w2, %3"
[(set_attr "v8type" "maddl") [(set_attr "v8type" "maddl")
(set_attr "type" "mul") (set_attr "type" "<su>mlal")
(set_attr "mode" "DI")] (set_attr "mode" "DI")]
) )
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment