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riscv-gcc-1
Commit 6a08ffca by Changpeng Fang Committed by Changpeng Fang
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Implementation of the pipeline description for Bulldozer (bdver1) 

	* gcc/config/i386/bdver1.md: New file.
	* gcc/config/i386/i386.md (include "bdver1.md"): Invoke the
	pipeline description for bdver1.
	(x86_sahf_1): Add "bdver1_decode" attribute.
	(*cmpfp_i_mixed): Likewise.
	(*cmpfp_i_sse): Likewise.
	(*cmpfp_i_i387): Likewise.
	(*cmpfp_iu_mixed): Likewise.
	(*cmpfp_iu_sse): Likewise.
	(*cmpfp_iu_387): Likewise.
	(*swap<mode>,*swap<mode>_1): Likewise.
	(fixuns_trunc<mode>hi2): Likewise.
	(fix_trunc<mode>si_sse): Likewise.
	(x86_fnstcw_1): Likewise.
	(x86_fldcw_1): Likewise.
	(*floatsi<mode>2_vector_mixed_with_temp): Likewise.
	(*floatsi<mode>2_vector_mixed): Likewise.
	(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_with_temp): Likewise.
	(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_interunit): Likewise.
	(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_nointerunit): Likewise.
	(*floatsi<mode>2_vector_sse_with_temp): Likewise.
	(*floatsi<mode>2_vector_sse): Likewise.
	(*float<SSEMODEI24:mode><MODEF:mode>2_sse_with_temp): Likewise.
	(*float<SSEMODEI24:mode><MODEF:mode>2_sse_interunit): Likewise.
	(*float<SSEMODEI24:mode><MODEF:mode>2_sse_nointerunit): Likewise.
	(*mul<mode>3_1): Likewise.
	(*mulsi3_1_zext): Likewise.
	(*mulhi3_1): Likewise.
	(*mulqi3_1): Likewise.
	(*<u>mul<mode><dwi>3_1): Likewise.
	(*<u>mulqihi3_1): Likewise.
	(*<s>muldi3_highpart_1): Likewise.
	(*<s>mulsi3_highpart_1): Likewise.
	(*<s>mulsi3_highpart_zext): Likewise.
	(x86_64_shld): Likewise.
	(x86_shld): Likewise.
	(x86_64_shrd): Likewise.
	(x86_shrd): Likewise.
	(sqrtxf2): Likewise.
	(sqrt_extend<mode>xf2_i387): Likewise.
	(*sqrt<mode>2_sse): Likewise.
	* gcc/config/i386/sse.md (sse_cvtsi2ss): Add "bdver1_decode" attribute.
	(sse_cvtsi2ssq): Likewise.
	(sse_cvtss2si): Likewise.
	(sse_cvtss2si_2): Likewise.
	(sse_cvtss2siq): Likewise.
	(sse_cvtss2siq_2): Likewise.
	(sse_cvttss2si): Likewise.
	(sse_cvttss2siq): Likewise.
	(sse2_cvtpi2pd): Likewise.
	(sse2_cvttpd2pi): Likewise.
	(sse2_cvtsi2sd): Likewise.
	(sse2_cvtsi2sdq): Likewise.
	(sse2_cvtsd2si): Likewise.
	(sse2_cvtsd2si_2): Likewise.
	(sse2_cvtsd2siq): Likewise.
	(sse2_cvtsd2siq_2): Likewise.
	(sse2_cvttsd2si): Likewise.
	(sse2_cvttsd2siq): Likewise.
	(*sse2_cvtpd2dq): Likewise.
	(*sse2_cvttpd2dq): Likewise.
	(sse2_cvtsd2ss): Likewise.
	(sse2_cvtss2sd): Likewise.
	(*sse2_cvtpd2ps): Likewise.
	(sse2_cvtps2pd): Likewise.

From-SVN: r165853
parent 07db7d35
Showing with 102 additions and 10 deletions
gcc/ChangeLog
2010-10-22 Changpeng Fang <changpeng.fang@amd.com>
* gcc/config/i386/bdver1.md: New file.
* gcc/config/i386/i386.md (include "bdver1.md"): Invoke the
pipeline description for bdver1.
(x86_sahf_1): Add "bdver1_decode" attribute.
(*cmpfp_i_mixed): Likewise.
(*cmpfp_i_sse): Likewise.
(*cmpfp_i_i387): Likewise.
(*cmpfp_iu_mixed): Likewise.
(*cmpfp_iu_sse): Likewise.
(*cmpfp_iu_387): Likewise.
(*swap<mode>,*swap<mode>_1): Likewise.
(fixuns_trunc<mode>hi2): Likewise.
(fix_trunc<mode>si_sse): Likewise.
(x86_fnstcw_1): Likewise.
(x86_fldcw_1): Likewise.
(*floatsi<mode>2_vector_mixed_with_temp): Likewise.
(*floatsi<mode>2_vector_mixed): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_with_temp): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_interunit): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_nointerunit): Likewise.
(*floatsi<mode>2_vector_sse_with_temp): Likewise.
(*floatsi<mode>2_vector_sse): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_sse_with_temp): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_sse_interunit): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_sse_nointerunit): Likewise.
(*mul<mode>3_1): Likewise.
(*mulsi3_1_zext): Likewise.
(*mulhi3_1): Likewise.
(*mulqi3_1): Likewise.
(*<u>mul<mode><dwi>3_1): Likewise.
(*<u>mulqihi3_1): Likewise.
(*<s>muldi3_highpart_1): Likewise.
(*<s>mulsi3_highpart_1): Likewise.
(*<s>mulsi3_highpart_zext): Likewise.
(x86_64_shld): Likewise.
(x86_shld): Likewise.
(x86_64_shrd): Likewise.
(x86_shrd): Likewise.
(sqrtxf2): Likewise.
(sqrt_extend<mode>xf2_i387): Likewise.
(*sqrt<mode>2_sse): Likewise.
* gcc/config/i386/sse.md (sse_cvtsi2ss): Add "bdver1_decode" attribute.
(sse_cvtsi2ssq): Likewise.
(sse_cvtss2si): Likewise.
(sse_cvtss2si_2): Likewise.
(sse_cvtss2siq): Likewise.
(sse_cvtss2siq_2): Likewise.
(sse_cvttss2si): Likewise.
(sse_cvttss2siq): Likewise.
(sse2_cvtpi2pd): Likewise.
(sse2_cvttpd2pi): Likewise.
(sse2_cvtsi2sd): Likewise.
(sse2_cvtsi2sdq): Likewise.
(sse2_cvtsd2si): Likewise.
(sse2_cvtsd2si_2): Likewise.
(sse2_cvtsd2siq): Likewise.
(sse2_cvtsd2siq_2): Likewise.
(sse2_cvttsd2si): Likewise.
(sse2_cvttsd2siq): Likewise.
(*sse2_cvtpd2dq): Likewise.
(*sse2_cvttpd2dq): Likewise.
(sse2_cvtsd2ss): Likewise.
(sse2_cvtss2sd): Likewise.
(*sse2_cvtpd2ps): Likewise.
(sse2_cvtps2pd): Likewise.
2010-10-22 Richard Guenther <rguenther@suse.de>
PR middle-end/46137
gcc/config/i386/sse.md
......@@ -2269,6 +2269,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "vector,double")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "bdver1_decode" "double,direct")
(set_attr "mode" "SF")])
(define_insn "*avx_cvtsi2ssq"
......@@ -2298,6 +2299,7 @@
(set_attr "prefix_rex" "1")
(set_attr "athlon_decode" "vector,double")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "bdver1_decode" "double,direct")
(set_attr "mode" "SF")])
(define_insn "sse_cvtss2si"
......@@ -2311,6 +2313,7 @@
"%vcvtss2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")])
......@@ -2324,6 +2327,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")])
......@@ -2339,6 +2343,7 @@
"%vcvtss2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
......@@ -2352,6 +2357,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
......@@ -2367,6 +2373,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")])
......@@ -2382,6 +2389,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
......@@ -2496,7 +2504,8 @@
[(set_attr "type" "ssecvt")
(set_attr "unit" "mmx")
(set_attr "prefix_data16" "1")
(set_attr "mode" "DI")])
(set_attr "mode" "DI")
(set_attr "bdver1_decode" "double")])
(define_insn "sse2_cvttpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
......@@ -2506,7 +2515,8 @@
[(set_attr "type" "ssecvt")
(set_attr "unit" "mmx")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(set_attr "mode" "TI")
(set_attr "bdver1_decode" "double")])
(define_insn "*avx_cvtsi2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
......@@ -2533,7 +2543,8 @@
[(set_attr "type" "sseicvt")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "amdfam10_decode" "vector,double")])
(set_attr "amdfam10_decode" "vector,double")
(set_attr "bdver1_decode" "double,direct")])
(define_insn "*avx_cvtsi2sdq"
[(set (match_operand:V2DF 0 "register_operand" "=x")
......@@ -2562,7 +2573,8 @@
(set_attr "prefix_rex" "1")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "amdfam10_decode" "vector,double")])
(set_attr "amdfam10_decode" "vector,double")
(set_attr "bdver1_decode" "double,direct")])
(define_insn "sse2_cvtsd2si"
[(set (match_operand:SI 0 "register_operand" "=r,r")
......@@ -2575,6 +2587,7 @@
"%vcvtsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")])
......@@ -2588,6 +2601,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")])
......@@ -2603,6 +2617,7 @@
"%vcvtsd2siq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
......@@ -2616,6 +2631,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
......@@ -2633,7 +2649,8 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")])
(define_insn "sse2_cvttsd2siq"
[(set (match_operand:DI 0 "register_operand" "=r,r")
......@@ -2648,7 +2665,8 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")])
(define_insn "avx_cvtdq2pd256"
[(set (match_operand:V4DF 0 "register_operand" "=x")
......@@ -2716,7 +2734,8 @@
(set_attr "prefix_data16" "0")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")])
(set_attr "amdfam10_decode" "double")
(set_attr "bdver1_decode" "double")])
(define_insn "avx_cvttpd2dq256"
[(set (match_operand:V4SI 0 "register_operand" "=x")
......@@ -2746,7 +2765,8 @@
[(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")])
(set_attr "amdfam10_decode" "double")
(set_attr "bdver1_decode" "double")])
(define_insn "*avx_cvtsd2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
......@@ -2775,6 +2795,7 @@
[(set_attr "type" "ssecvt")
(set_attr "athlon_decode" "vector,double")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "bdver1_decode" "direct,direct")
(set_attr "mode" "SF")])
(define_insn "*avx_cvtss2sd"
......@@ -2805,6 +2826,7 @@
"cvtss2sd\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "bdver1_decode" "direct,direct")
(set_attr "mode" "DF")])
(define_insn "avx_cvtpd2ps256"
......@@ -2839,7 +2861,8 @@
(set_attr "prefix_data16" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")
(set_attr "amdfam10_decode" "double")])
(set_attr "amdfam10_decode" "double")
(set_attr "bdver1_decode" "double")])
(define_insn "avx_cvtps2pd256"
[(set (match_operand:V4DF 0 "register_operand" "=x")
......@@ -2875,7 +2898,8 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V2DF")
(set_attr "prefix_data16" "0")
(set_attr "amdfam10_decode" "direct")])
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "double")])
(define_expand "vec_unpacks_hi_v4sf"
[(set (match_dup 2)
......
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