[AArch64][SVE] Add ABS support

For some reason we missed ABS out of the list of supported integer
operations when adding the SVE port initially.

2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (SVE_INT_UNARY, fp_int_op): Add abs.
	(SVE_FP_UNARY): Sort.

gcc/testsuite/
	* gcc.target/aarch64/pr64946.c: Force nosve.
	* gcc.target/aarch64/ssadv16qi.c: Likewise.
	* gcc.target/aarch64/usadv16qi.c: Likewise.
	* gcc.target/aarch64/vect-abs-compile.c: Likewise.
	* gcc.target/aarch64/sve/abs_1.c: New test.

From-SVN: r267304

gcc/ChangeLog

 2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>
 
+	* config/aarch64/iterators.md (SVE_INT_UNARY, fp_int_op): Add abs.
+	(SVE_FP_UNARY): Sort.
+
+2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>
+
 	* config/aarch64/aarch64-sve.md (*cond_<optab><mode>_4): Use
 	sve_fmla_op rather than sve_fmad_op for the movprfx alternative.
 

gcc/config/aarch64/iterators.md

@@ -1209,10 +1209,10 @@
 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
 
 ;; SVE integer unary operations.
-(define_code_iterator SVE_INT_UNARY [neg not popcount])
+(define_code_iterator SVE_INT_UNARY [abs neg not popcount])
 
 ;; SVE floating-point unary operations.
-(define_code_iterator SVE_FP_UNARY [neg abs sqrt])
+(define_code_iterator SVE_FP_UNARY [abs neg sqrt])
 
 ;; SVE integer binary operations.
 (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
@@ -1401,6 +1401,7 @@
 			      (mult "mul")
 			      (div "sdiv")
 			      (udiv "udiv")
+			      (abs "abs")
 			      (neg "neg")
 			      (smin "smin")
 			      (smax "smax")

gcc/testsuite/ChangeLog

 2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>
 
+	* gcc.target/aarch64/pr64946.c: Force nosve.
+	* gcc.target/aarch64/ssadv16qi.c: Likewise.
+	* gcc.target/aarch64/usadv16qi.c: Likewise.
+	* gcc.target/aarch64/vect-abs-compile.c: Likewise.
+	* gcc.target/aarch64/sve/abs_1.c: New test.
+
+2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>
+
 	* gcc.target/aarch64/sve/fmla_2.c: New test.
 	* gcc.target/aarch64/sve/fmla_2_run.c: Likewise
 

gcc/testsuite/gcc.target/aarch64/pr64946.c

-
 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 signed char a[100],b[100];
 void absolute_s8 (void)
 {

gcc/testsuite/gcc.target/aarch64/ssadv16qi.c

 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 #define N 1024
 
 signed char pix1[N], pix2[N];

gcc/testsuite/gcc.target/aarch64/sve/abs_1.c

+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <stdint.h>
+
+#define DO_OPS(TYPE)					\
+void vneg_##TYPE (TYPE *dst, TYPE *src, int count)	\
+{							\
+  for (int i = 0; i < count; ++i)			\
+    dst[i] = src[i] < 0 ? -src[i] : src[i];		\
+}
+
+DO_OPS (int8_t)
+DO_OPS (int16_t)
+DO_OPS (int32_t)
+DO_OPS (int64_t)
+
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 1 } } */

gcc/testsuite/gcc.target/aarch64/usadv16qi.c

 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 #define N 1024
 
 unsigned char pix1[N], pix2[N];

gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c

-
 /* { dg-do compile } */
 /* { dg-options "-O3 -fno-vect-cost-model" } */
 
+#pragma GCC target "+nosve"
+
 #define N 16
 
 #include "vect-abs.x"