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riscv-gcc-1
Commit 6975bd2c by Kazuhiro Inaoka Committed by Nick Clifton
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m32r.h: Add support for m32r2 processor. 

* config/m32r/m32r.h: Add support for m32r2 processor.  Including
  a new command line option -m32r2 to select it.
* config/m32r/m32r.c: Add support for the new processor variant.
* config/m32r/m32r.md: Likewise.
* config/m32r/t-m32r: Add m32r2 multilibs.
* doc/invoke.texi: Document the new command line switch.

From-SVN: r74473
parent 3a7ab7e8
Showing with 44 additions and 13 deletions
gcc/ChangeLog
2003-12-09 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* config/m32r/m32r.h: Add support for m32r2 processor. Including
a new command line option -m32r2 to select it.
* config/m32r/m32r.c: Add support for the new processor variant.
* config/m32r/m32r.md: Likewise.
* config/m32r/t-m32r: Add m32r2 multilibs.
* doc/invoke.texi: Document the new command line switch.
2003-12-08 Kazu Hirata <kazu@cs.umass.edu>
* defaults.h (LOCAL_REGNO): Give the default definition.
......
gcc/config.gcc
......@@ -659,7 +659,7 @@ arm*-*-netbsd*)
use_collect2=yes
;;
arm*-*-linux*) # ARM GNU/Linux with ELF
tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h arm/linux-gas.h arm/linux-elf.h"
tm_file="dbxelf.h elfos.h linux.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h arm/linux-gas.h arm/linux-elf.h"
tmake_file="t-slibgcc-elf-ver t-linux arm/t-linux"
extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
gnu_ld=yes
......
gcc/config/arm/linux-elf.h
......@@ -47,6 +47,7 @@
#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
/* Now we define the strings used to build the spec file. */
#undef LIB_SPEC
#define LIB_SPEC \
"%{pthread:-lpthread} \
%{shared:-lc} \
......
gcc/config/m32r/m32r.h
......@@ -42,14 +42,18 @@ Boston, MA 02111-1307, USA. */
/* M32R/X overrides. */
/* Print subsidiary information on the compiler version in use. */
#define TARGET_VERSION fprintf (stderr, " (m32r/x)");
#define TARGET_VERSION fprintf (stderr, " (m32r/x/2)");
/* Additional flags for the preprocessor. */
#define CPP_CPU_SPEC "%{m32rx:-D__M32RX__} %{m32r:-U__M32RX__}"
#define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
%{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
%{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
"
/* Assembler switches. */
#define ASM_CPU_SPEC \
"%{m32r} %{m32rx} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
"%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
/* Use m32rx specific crt0/crtinit/crtfini files. */
#define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
......@@ -58,7 +62,8 @@ Boston, MA 02111-1307, USA. */
/* Extra machine dependent switches. */
#define SUBTARGET_SWITCHES \
{ "32rx", TARGET_M32RX_MASK, "Compile for the m32rx" }, \
{ "32r", -TARGET_M32RX_MASK, "" },
{ "32r2", TARGET_M32R2_MASK, "Compile for the m32r2" }, \
{ "32r", -(TARGET_M32RX_MASK+TARGET_M32R2_MASK), "" },
/* Define this macro as a C expression for the initializer of an array of
strings to tell the driver program which options are defaults for this
......@@ -223,6 +228,12 @@ extern int target_flags;
#undef TARGET_M32R
#define TARGET_M32R (! TARGET_M32RX)
/* Support extended instruction set of m32r2. */
#define TARGET_M32R2_MASK (1 << 6)
#define TARGET_M32R2 (target_flags & TARGET_M32RX_MASK)
#undef TARGET_M32R
#define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
......
gcc/config/m32r/m32r.md
......@@ -72,8 +72,12 @@
(define_attr "m32rx" "no,yes"
(const (symbol_ref "(TARGET_M32RX != 0)")))
(define_attr "m32r2" "no,yes"
(const (symbol_ref "(TARGET_M32R2 != 0)")))
(define_attr "m32rx_pipeline" "either,s,o,long,m32r"
(cond [(eq_attr "m32rx" "no")
(cond [(and (eq_attr "m32rx" "no")
(eq_attr "m32r2" "no"))
(const_string "m32r")
(eq_attr "insn_size" "!short")
......@@ -1180,7 +1184,7 @@
[(set (reg:SI 17)
(eq:SI (match_operand:SI 0 "register_operand" "r,r")
(match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
"TARGET_M32RX"
"TARGET_M32RX || TARGET_M32R2"
"@
cmpeq %0, %1
cmpz %0"
......@@ -1612,7 +1616,7 @@
if (! register_operand (op1, mode))
op1 = force_reg (mode, op1);
if (TARGET_M32RX)
if (TARGET_M32RX || TARGET_M32R2)
{
if (! reg_or_zero_operand (op2, mode))
op2 = force_reg (mode, op2);
......@@ -1638,7 +1642,7 @@
(eq:SI (match_operand:SI 1 "register_operand" "%r")
(match_operand:SI 2 "reg_or_zero_operand" "rP")))
(clobber (reg:SI 17))]
"TARGET_M32RX"
"TARGET_M32RX || TARGET_M32R2"
"#"
[(set_attr "type" "multi")
(set_attr "length" "6")])
......@@ -1648,7 +1652,7 @@
(eq:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_zero_operand" "")))
(clobber (reg:SI 17))]
"TARGET_M32RX"
"TARGET_M32RX || TARGET_M32R2"
[(set (reg:SI 17)
(eq:SI (match_dup 1)
(match_dup 2)))
......
gcc/config/m32r/t-m32r
......@@ -41,14 +41,16 @@ $(T)crtfini.o: $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
-o $(T)crtfini.o
m32rx:
mkdir $@
m32r2:
mkdir $@
# -mmodel={small,medium} requires separate libraries.
# We don't build libraries for the large model, instead we use the medium
# libraries. The only difference is that the large model can handle jumps
# more than 26 signed bits away.
MULTILIB_OPTIONS = mmodel=small/mmodel=medium m32r/m32rx
MULTILIB_DIRNAMES = small medium m32r m32rx
MULTILIB_OPTIONS = mmodel=small/mmodel=medium m32r/m32rx/m32r2
MULTILIB_DIRNAMES = small medium m32r m32rx m32r2
MULTILIB_MATCHES = mmodel?medium=mmodel?large
# Set MULTILIB_EXTRA_OPTS so shipped libraries have small data in .sdata and
......
gcc/doc/invoke.texi
......@@ -400,7 +400,7 @@ in the following sections.
-mno-crt0 -mrelax}
@emph{M32R/D Options}
@gccoptlist{-m32rx -m32r -mcode-model=@var{model-type} @gol
@gccoptlist{-m32r2 -m32rx -m32r -mcode-model=@var{model-type} @gol
-msdata=@var{sdata-type} -G @var{num}}
@emph{M88K Options}
......@@ -6840,6 +6840,10 @@ This option makes symbolic debugging impossible.
These @option{-m} options are defined for Mitsubishi M32R/D architectures:
@table @gcctabopt
@item -m32r2
@opindex m32r2
Generate code for the M32R/2@.
@item -m32rx
@opindex m32rx
Generate code for the M32R/X@.
......
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