Commit 696a2ca1 by Jim Wilson

Fix ICE with long double after float HFA.

PR target/19357
* config/ia64/ia64.md (movxf): Handle general register source.  Adjust
comment to document why.
* gcc.c-torture/compile/pr19357.c: New test.

From-SVN: r93809
parent 115a33c2
2005-01-17 James E Wilson <wilson@specifixinc.com>
PR target/19357
* config/ia64/ia64.md (movxf): Handle general register source. Adjust
comment to document why.
2005-01-17 Richard Henderson <rth@redhat.com> 2005-01-17 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (smaxv4sf3_finite, sse_vmsmaxv4sf3_finite, * config/i386/sse.md (smaxv4sf3_finite, sse_vmsmaxv4sf3_finite,
......
...@@ -685,10 +685,12 @@ ...@@ -685,10 +685,12 @@
if (GET_CODE (op0) == SUBREG) if (GET_CODE (op0) == SUBREG)
op0 = SUBREG_REG (op0); op0 = SUBREG_REG (op0);
/* We must support XFmode loads into general registers for stdarg/vararg /* We must support XFmode loads into general registers for stdarg/vararg,
and unprototyped calls. We split them into DImode loads for convenience. unprototyped calls, and a rare case where a long double is passed as
We don't need XFmode stores from general regs, because a stdarg/vararg an argument after a float HFA fills the FP registers. We split them into
routine does a block store to memory of unnamed arguments. */ DImode loads for convenience. We also need to support XFmode stores
for the last case. This case does not happen for stdarg/vararg routines,
because we do a block store to memory of unnamed arguments. */
if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0))) if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
{ {
...@@ -708,7 +710,6 @@ ...@@ -708,7 +710,6 @@
if (GET_CODE (op1) == SUBREG) if (GET_CODE (op1) == SUBREG)
op1 = SUBREG_REG (op1); op1 = SUBREG_REG (op1);
else else
/* ??? Maybe we should make a SUBREG here? */
op1 = gen_rtx_REG (TImode, REGNO (op1)); op1 = gen_rtx_REG (TImode, REGNO (op1));
emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1); emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
...@@ -743,6 +744,40 @@ ...@@ -743,6 +744,40 @@
abort (); abort ();
} }
if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
{
/* We're hoping to transform everything that deals with XFmode
quantities and GR registers early in the compiler. */
if (no_new_pseudos)
abort ();
/* Op0 can't be a GR_REG here, as that case is handled above.
If op0 is a register, then we spill op1, so that we now have a
MEM operand. This requires creating an XFmode subreg of a TImode reg
to force the spill. */
if (register_operand (operands[0], XFmode))
{
rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
op1 = gen_rtx_SUBREG (XFmode, op1, 0);
operands[1] = spill_xfmode_operand (op1, 0);
}
else if (GET_CODE (operands[0]) == MEM)
{
rtx in[2];
in[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]));
in[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
DONE;
}
else
abort ();
}
if (! reload_in_progress && ! reload_completed) if (! reload_in_progress && ! reload_completed)
{ {
operands[1] = spill_xfmode_operand (operands[1], 0); operands[1] = spill_xfmode_operand (operands[1], 0);
......
2005-01-17 James E. Wilson <wilson@specifixinc.com>
PR target/19357
* gcc.c-torture/compile/pr19357.c: New test.
2005-01-17 Ian Lance Taylor <ian@airs.com> 2005-01-17 Ian Lance Taylor <ian@airs.com>
PR c/5675 PR c/5675
......
/* This generated an ICE for an ia64-linux target. */
struct f {
float f[8];
};
long double ftest(struct f arg1, long double arg2) {
return arg2;
}
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