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Commit 6960bf55 by Alan Lawrence Committed by Alan Lawrence
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[AArch64 array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg aarch64_st/ld expands 

	* config/aarch64/aarch64-simd.md
	(aarch64_ld2<mode>_dreg VD & DX, aarch64_st2<mode>_dreg VD & DX ):
	Change all TImode operands to BLKmode.
	(aarch64_ld3<mode>_dreg VD & DX, aarch64_st3<mode>_dreg VD & DX):
	Change all EImode operands to BLKmode.
	(aarch64_ld4<mode>_dreg VD & DX, aarch64_st4<mode>_dreg VD & DX):
	Change all OImode operands to BLKmode.

	(aarch64_ld<VSTRUCT:nregs><VDC:mode>): Generate MEM rtx with BLKmode
	and call set_mem_size.
	(aarch64_st<VSTRUCT:nregs><VDC:mode>): Likewise

	* config/aarch64/iterators.md (VSTRUCT_DREG): Remove.

From-SVN: r227782
parent d30ab8e0
Showing with 50 additions and 30 deletions
gcc/ChangeLog
2015-09-15 Alan Lawrence <alan.lawrence@arm.com> 2015-09-15 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_ld2<mode>_dreg VD & DX, aarch64_st2<mode>_dreg VD & DX ):
Change all TImode operands to BLKmode.
(aarch64_ld3<mode>_dreg VD & DX, aarch64_st3<mode>_dreg VD & DX):
Change all EImode operands to BLKmode.
(aarch64_ld4<mode>_dreg VD & DX, aarch64_st4<mode>_dreg VD & DX):
Change all OImode operands to BLKmode.
(aarch64_ld<VSTRUCT:nregs><VDC:mode>): Generate MEM rtx with BLKmode
and call set_mem_size.
(aarch64_st<VSTRUCT:nregs><VDC:mode>): Likewise.
* config/aarch64/iterators.md (VSTRUCT_DREG): Remove.
2015-09-15 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): Rename * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): Rename
to... to...
(aarch64_vec_store_lanesoi_lane<mode>): ...this. (aarch64_vec_store_lanesoi_lane<mode>): ...this.
......
gcc/config/aarch64/aarch64-simd.md
...@@ -4425,8 +4425,9 @@ ...@@ -4425,8 +4425,9 @@
(subreg:OI (subreg:OI
(vec_concat:<VRL2> (vec_concat:<VRL2>
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:VD [(match_operand:TI 1 "aarch64_simd_struct_operand" "Utv")] (unspec:VD
UNSPEC_LD2) [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD2)
(vec_duplicate:VD (const_int 0))) (vec_duplicate:VD (const_int 0)))
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:VD [(match_dup 1)] (unspec:VD [(match_dup 1)]
...@@ -4442,8 +4443,9 @@ ...@@ -4442,8 +4443,9 @@
(subreg:OI (subreg:OI
(vec_concat:<VRL2> (vec_concat:<VRL2>
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:DX [(match_operand:TI 1 "aarch64_simd_struct_operand" "Utv")] (unspec:DX
UNSPEC_LD2) [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD2)
(const_int 0)) (const_int 0))
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:DX [(match_dup 1)] (unspec:DX [(match_dup 1)]
...@@ -4460,8 +4462,9 @@ ...@@ -4460,8 +4462,9 @@
(vec_concat:<VRL3> (vec_concat:<VRL3>
(vec_concat:<VRL2> (vec_concat:<VRL2>
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:VD [(match_operand:EI 1 "aarch64_simd_struct_operand" "Utv")] (unspec:VD
UNSPEC_LD3) [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD3)
(vec_duplicate:VD (const_int 0))) (vec_duplicate:VD (const_int 0)))
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:VD [(match_dup 1)] (unspec:VD [(match_dup 1)]
...@@ -4482,8 +4485,9 @@ ...@@ -4482,8 +4485,9 @@
(vec_concat:<VRL3> (vec_concat:<VRL3>
(vec_concat:<VRL2> (vec_concat:<VRL2>
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:DX [(match_operand:EI 1 "aarch64_simd_struct_operand" "Utv")] (unspec:DX
UNSPEC_LD3) [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD3)
(const_int 0)) (const_int 0))
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:DX [(match_dup 1)] (unspec:DX [(match_dup 1)]
...@@ -4504,8 +4508,9 @@ ...@@ -4504,8 +4508,9 @@
(vec_concat:<VRL4> (vec_concat:<VRL4>
(vec_concat:<VRL2> (vec_concat:<VRL2>
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:VD [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")] (unspec:VD
UNSPEC_LD4) [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD4)
(vec_duplicate:VD (const_int 0))) (vec_duplicate:VD (const_int 0)))
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:VD [(match_dup 1)] (unspec:VD [(match_dup 1)]
...@@ -4531,8 +4536,9 @@ ...@@ -4531,8 +4536,9 @@
(vec_concat:<VRL4> (vec_concat:<VRL4>
(vec_concat:<VRL2> (vec_concat:<VRL2>
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:DX [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")] (unspec:DX
UNSPEC_LD4) [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD4)
(const_int 0)) (const_int 0))
(vec_concat:<VDBL> (vec_concat:<VDBL>
(unspec:DX [(match_dup 1)] (unspec:DX [(match_dup 1)]
...@@ -4558,8 +4564,8 @@ ...@@ -4558,8 +4564,8 @@
(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD" "TARGET_SIMD"
{ {
machine_mode mode = <VSTRUCT:VSTRUCT_DREG>mode; rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
rtx mem = gen_rtx_MEM (mode, operands[1]); set_mem_size (mem, <VSTRUCT:nregs> * 8);
emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg (operands[0], mem)); emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg (operands[0], mem));
DONE; DONE;
...@@ -4791,8 +4797,8 @@ ...@@ -4791,8 +4797,8 @@
) )
(define_insn "aarch64_st2<mode>_dreg" (define_insn "aarch64_st2<mode>_dreg"
[(set (match_operand:TI 0 "aarch64_simd_struct_operand" "=Utv") [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:TI [(match_operand:OI 1 "register_operand" "w") (unspec:BLK [(match_operand:OI 1 "register_operand" "w")
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST2))] UNSPEC_ST2))]
"TARGET_SIMD" "TARGET_SIMD"
...@@ -4801,8 +4807,8 @@ ...@@ -4801,8 +4807,8 @@
) )
(define_insn "aarch64_st2<mode>_dreg" (define_insn "aarch64_st2<mode>_dreg"
[(set (match_operand:TI 0 "aarch64_simd_struct_operand" "=Utv") [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:TI [(match_operand:OI 1 "register_operand" "w") (unspec:BLK [(match_operand:OI 1 "register_operand" "w")
(unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST2))] UNSPEC_ST2))]
"TARGET_SIMD" "TARGET_SIMD"
...@@ -4811,8 +4817,8 @@ ...@@ -4811,8 +4817,8 @@
) )
(define_insn "aarch64_st3<mode>_dreg" (define_insn "aarch64_st3<mode>_dreg"
[(set (match_operand:EI 0 "aarch64_simd_struct_operand" "=Utv") [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:EI [(match_operand:CI 1 "register_operand" "w") (unspec:BLK [(match_operand:CI 1 "register_operand" "w")
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST3))] UNSPEC_ST3))]
"TARGET_SIMD" "TARGET_SIMD"
...@@ -4821,8 +4827,8 @@ ...@@ -4821,8 +4827,8 @@
) )
(define_insn "aarch64_st3<mode>_dreg" (define_insn "aarch64_st3<mode>_dreg"
[(set (match_operand:EI 0 "aarch64_simd_struct_operand" "=Utv") [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:EI [(match_operand:CI 1 "register_operand" "w") (unspec:BLK [(match_operand:CI 1 "register_operand" "w")
(unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST3))] UNSPEC_ST3))]
"TARGET_SIMD" "TARGET_SIMD"
...@@ -4831,8 +4837,8 @@ ...@@ -4831,8 +4837,8 @@
) )
(define_insn "aarch64_st4<mode>_dreg" (define_insn "aarch64_st4<mode>_dreg"
[(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv") [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:OI [(match_operand:XI 1 "register_operand" "w") (unspec:BLK [(match_operand:XI 1 "register_operand" "w")
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST4))] UNSPEC_ST4))]
"TARGET_SIMD" "TARGET_SIMD"
...@@ -4841,8 +4847,8 @@ ...@@ -4841,8 +4847,8 @@
) )
(define_insn "aarch64_st4<mode>_dreg" (define_insn "aarch64_st4<mode>_dreg"
[(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv") [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:OI [(match_operand:XI 1 "register_operand" "w") (unspec:BLK [(match_operand:XI 1 "register_operand" "w")
(unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST4))] UNSPEC_ST4))]
"TARGET_SIMD" "TARGET_SIMD"
...@@ -4856,8 +4862,8 @@ ...@@ -4856,8 +4862,8 @@
(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD" "TARGET_SIMD"
{ {
machine_mode mode = <VSTRUCT:VSTRUCT_DREG>mode; rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
rtx mem = gen_rtx_MEM (mode, operands[0]); set_mem_size (mem, <VSTRUCT:nregs> * 8);
emit_insn (gen_aarch64_st<VSTRUCT:nregs><VDC:mode>_dreg (mem, operands[1])); emit_insn (gen_aarch64_st<VSTRUCT:nregs><VDC:mode>_dreg (mem, operands[1]));
DONE; DONE;
......
gcc/config/aarch64/iterators.md
...@@ -594,8 +594,6 @@ ...@@ -594,8 +594,6 @@
(V2SI "V16SI") (V2SF "V16SF") (V2SI "V16SI") (V2SF "V16SF")
(DI "V8DI") (DF "V8DF")]) (DI "V8DI") (DF "V8DF")])
(define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")])
;; Mode of pair of elements for each vector mode, to define transfer ;; Mode of pair of elements for each vector mode, to define transfer
;; size for structure lane/dup loads and stores. ;; size for structure lane/dup loads and stores.
(define_mode_attr V_TWO_ELEM [(V8QI "HI") (V16QI "HI") (define_mode_attr V_TWO_ELEM [(V8QI "HI") (V16QI "HI")
......
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