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riscv-gcc-1
Commit 68944452 by Jeff Law
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pa.md (abssi2): New pattern. 

	* pa.md (abssi2): New pattern.

	* pa.c (secondary_reload_class): Loads from reg+d addresses into
	FP registers don't need secondary reloads.
	* pa.h: Delete soem #if 0 code.  Update some comments.
	(EXTRA_CONSTRAINT, case 'Q'): Only accept valid memory addresses.

        * pa.h (RTX_COSTS): Tege's rewrite.

	* pa.c (hppa_legitimize_address): Generate unscaled indexed
	addressing for (plus (symbol_ref) (reg)).
	(emit_move_sequence): Set REGNO_POINTER_FLAG appropriately
	to encourage unscaled indexing modes.
	(basereg_operand): New function for unscaled index address support.
	* pa.md (unscaled indexing patterns): New patterns for unscaled
	index address support.

	* pa.h (MOVE_RATIO): Define.
	* pa.md (movstrsi expander): Refine tests for when to use the
	library routine instead of an inlined loop copy.  Provide an
	additional scratch register for use in the inlined loop copy.
	(movstrsi_internal): Name the pattern for ease of use.  Add
	additional scratch register.
	* pa.c (output_block_move): Greatly simplify.  Use 2X unrolled
	copy loops to improve performance.
	(compute_movstrsi_length): Corresponding changes.

	* pa.c (print_operand): Handle 'y' case for reversed FP
	comparisons.  Delete some #if 0 code.  Fix various comment typos.
	* pa.md (fcmp patterns): Try and reverse the comparison to avoid
	useless add,tr insns.

From-SVN: r10609
parent 926d1ca5
Showing with 27 additions and 57 deletions
gcc/config/pa/pa.h
......@@ -1309,10 +1309,6 @@ extern struct rtx_def *hppa_builtin_saveregs ();
these things in insns and then not re-recognize the insns, causing
constrain_operands to fail.
Also note `Q' accepts any memory operand during the reload pass.
This includes out-of-range displacements in reg+d addressing.
This makes for better code. (??? For 2.5 address this issue).
`R' is unused.
`S' is unused.
......@@ -1321,8 +1317,6 @@ extern struct rtx_def *hppa_builtin_saveregs ();
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? \
(IS_RELOADING_PSEUDO_P (OP) \
|| (GET_CODE (OP) == MEM \
&& reload_in_progress) \
|| (GET_CODE (OP) == MEM \
&& memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
&& ! symbolic_memory_operand (OP, VOIDmode))) \
......@@ -1571,6 +1565,11 @@ while (0)
in one reasonably fast instruction. */
#define MOVE_MAX 8
/* Higher than the default as we prefer to use simple move insns
(better scheduling and delay slot filling) and because our
built-in block move is really a 2X unrolled loop. */
#define MOVE_RATIO 4
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
......@@ -1685,22 +1684,28 @@ while (0)
switch on CODE. The purpose for the cost of MULT is to encourage
`synth_mult' to find a synthetic multiply when reasonable. */
#define RTX_COSTS(X,CODE,OUTER_CODE) \
case MULT: \
return (TARGET_SNAKE && ! TARGET_DISABLE_FPREGS \
&& ! TARGET_SOFT_FLOAT \
? COSTS_N_INSNS (8) : COSTS_N_INSNS (20)); \
case DIV: \
case UDIV: \
case MOD: \
case UMOD: \
return COSTS_N_INSNS (60); \
case PLUS: \
if (GET_CODE (XEXP (X, 0)) == MULT \
&& shadd_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
+ rtx_cost (XEXP (X, 1), OUTER_CODE)); \
break;
#define RTX_COSTS(X,CODE,OUTER_CODE) \
case MULT: \
if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
return COSTS_N_INSNS (3); \
return (TARGET_SNAKE && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT) \
? COSTS_N_INSNS (8) : COSTS_N_INSNS (20); \
case DIV: \
if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
return COSTS_N_INSNS (14); \
case UDIV: \
case MOD: \
case UMOD: \
return COSTS_N_INSNS (60); \
case PLUS: /* this includes shNadd insns */ \
case MINUS: \
if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
return COSTS_N_INSNS (3); \
return COSTS_N_INSNS (1); \
case ASHIFT: \
case ASHIFTRT: \
case LSHIFTRT: \
return COSTS_N_INSNS (1);
/* Adjust the cost of dependencies. */
......@@ -2154,41 +2159,6 @@ extern struct rtx_def *legitimize_pic_address ();
extern struct rtx_def *gen_cmp_fp ();
extern void hppa_encode_label ();
#if 0
#define PREDICATE_CODES \
{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
{"arith_operand", {SUBREG, REG, CONST_INT}}, \
{"arith32_operand", {SUBREG, REG, CONST_INT}}, \
{"arith11_operand", {SUBREG, REG, CONST_INT}}, \
{"arith5_operand", {SUBREG, REG, CONST_INT}}, \
{"pre_cint_operand", {CONST_INT}}, \
{"post_cint_operand", {CONST_INT}}, \
{"int5_operand", {CONST_INT}}, \
{"uint5_operand", {CONST_INT}}, \
{"uint32_operand", {CONST_INT}}, \
{"int11_operand", {CONST_INT}}, \
{"and_operand", {SUBREG, REG, CONST_INT}}, \
{"ior_operand", {CONST_INT}}, \
{"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \
{"lhs_lshift_cint_operand", {CONST_INT}}, \
{"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \
{"shadd_operand", {CONST_INT}}, \
{"eq_neq_comparison_operator", {EQ, NE}}, \
{"movb_comparison_operator", {EQ, NE, LT, GE}}, \
{"pc_or_label_operand", {LABEL_REF, PC}}, \
{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
{"move_operand", {SUBREG, REG, CONST_INT, MEM}}, \
{"pic_label_operand", {LABEL_REF, CONST}}, \
{"function_label_operand", {SYMBOL_REF}}, \
{"reg_or_0_or_nonsymb_mem_operand", {SUBREG, REG, CONST_INT, \
CONST_DOUBLE, MEM}}, \
{"div_operand", {REG, CONST_INT}}, \
{"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST_INT, \
CONST_DOUBLE, CONST, HIGH}},
#endif
/* We want __gcc_plt_call to appear in every program built by
gcc, so we make a reference to it out of __main.
We use the asm statement to fool the optimizer into not
......
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