Commit 67f783cb by Alexander Ivchenko Committed by Kirill Yukhin

i386.md (multdiv): New.

        * config/i386/i386.md (multdiv): New.
        (multdiv_mnemonic): Ditto.
        * config/i386/sse.md (<sse>_vmmul<mode>3): Changed to...
        (<sse>_vm<multdiv_mnemonic><mode>3): This.
        (<sse>_vmdiv<mode>3): Removed.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
Co-Authored-By: Sergey Lega <sergey.s.lega@intel.com>

From-SVN: r203432
parent ec5e777c
...@@ -8,6 +8,22 @@ ...@@ -8,6 +8,22 @@
Kirill Yukhin <kirill.yukhin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/i386.md (multdiv): New.
(multdiv_mnemonic): Ditto.
* config/i386/sse.md (<sse>_vmmul<mode>3): Changed to...
(<sse>_vm<multdiv_mnemonic><mode>3): This.
(<sse>_vmdiv<mode>3): Removed.
2013-10-11 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/sse.md (V): Extended with wider modes. * config/i386/sse.md (V): Extended with wider modes.
(VF2): Ditto. (VF2): Ditto.
(ssehalfvecmode): Ditto. (ssehalfvecmode): Ditto.
......
...@@ -746,6 +746,8 @@ ...@@ -746,6 +746,8 @@
(define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus]) (define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus])
(define_code_iterator multdiv [mult div])
;; Base name for define_insn ;; Base name for define_insn
(define_code_attr plusminus_insn (define_code_attr plusminus_insn
[(plus "add") (ss_plus "ssadd") (us_plus "usadd") [(plus "add") (ss_plus "ssadd") (us_plus "usadd")
...@@ -757,6 +759,8 @@ ...@@ -757,6 +759,8 @@
(minus "sub") (ss_minus "subs") (us_minus "subus")]) (minus "sub") (ss_minus "subs") (us_minus "subus")])
(define_code_attr plusminus_carry_mnemonic (define_code_attr plusminus_carry_mnemonic
[(plus "adc") (minus "sbb")]) [(plus "adc") (minus "sbb")])
(define_code_attr multdiv_mnemonic
[(mult "mul") (div "div")])
;; Mark commutative operators as such in constraints. ;; Mark commutative operators as such in constraints.
(define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%") (define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%")
......
...@@ -1061,21 +1061,22 @@ ...@@ -1061,21 +1061,22 @@
(set_attr "btver2_decode" "direct,double") (set_attr "btver2_decode" "direct,double")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_insn "<sse>_vmmul<mode>3" (define_insn "<sse>_vm<multdiv_mnemonic><mode>3"
[(set (match_operand:VF_128 0 "register_operand" "=x,v") [(set (match_operand:VF_128 0 "register_operand" "=x,v")
(vec_merge:VF_128 (vec_merge:VF_128
(mult:VF_128 (multdiv:VF_128
(match_operand:VF_128 1 "register_operand" "0,v") (match_operand:VF_128 1 "register_operand" "0,v")
(match_operand:VF_128 2 "nonimmediate_operand" "xm,vm")) (match_operand:VF_128 2 "nonimmediate_operand" "xm,vm"))
(match_dup 1) (match_dup 1)
(const_int 1)))] (const_int 1)))]
"TARGET_SSE" "TARGET_SSE"
"@ "@
mul<ssescalarmodesuffix>\t{%2, %0|%0, %<iptr>2} <multdiv_mnemonic><ssescalarmodesuffix>\t{%2, %0|%0, %<iptr>2}
vmul<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %<iptr>2}" v<multdiv_mnemonic><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %<iptr>2}"
[(set_attr "isa" "noavx,avx") [(set_attr "isa" "noavx,avx")
(set_attr "type" "ssemul") (set_attr "type" "sse<multdiv_mnemonic>")
(set_attr "prefix" "orig,vex") (set_attr "prefix" "orig,maybe_evex")
(set_attr "btver2_decode" "direct,double")
(set_attr "mode" "<ssescalarmode>")]) (set_attr "mode" "<ssescalarmode>")])
(define_expand "div<mode>3" (define_expand "div<mode>3"
...@@ -1118,24 +1119,6 @@ ...@@ -1118,24 +1119,6 @@
(set_attr "prefix" "orig,vex") (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_insn "<sse>_vmdiv<mode>3"
[(set (match_operand:VF_128 0 "register_operand" "=x,v")
(vec_merge:VF_128
(div:VF_128
(match_operand:VF_128 1 "register_operand" "0,v")
(match_operand:VF_128 2 "nonimmediate_operand" "xm,vm"))
(match_dup 1)
(const_int 1)))]
"TARGET_SSE"
"@
div<ssescalarmodesuffix>\t{%2, %0|%0, %<iptr>2}
vdiv<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %<iptr>2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssediv")
(set_attr "prefix" "orig,vex")
(set_attr "btver2_decode" "direct,double")
(set_attr "mode" "<ssescalarmode>")])
(define_insn "<sse>_rcp<mode>2" (define_insn "<sse>_rcp<mode>2"
[(set (match_operand:VF1_128_256 0 "register_operand" "=x") [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
(unspec:VF1_128_256 (unspec:VF1_128_256
......
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