alpha: Unify SF, DF, QI, HI, SI mode moves with enabled attribute.

For floating-point, this involves in addition conditionalizing the
definition of the "f" register constraint.

From-SVN: r171436

gcc/ChangeLog

 2011-02-24  Richard Henderson  <rth@redhat.com>
 
+	* config/alpha/alpha.md (attribute isa): Add vms.
+	(attribute enabled): Handle it.
+	(*movsf): Merge *movsf_{nofix,fix,nofp}.
+	(*movdf): Merge *movdf_{nofix,fix,nofp}.
+	(*movtf): Rename from *movtf_internal for consistency.
+	(*movsi): Merge with *movsi_nt_vms.
+	(*movhi): Merge *movhi_nobwx, *movhi_bwx.
+	(*movqi): Merge *movqi_nobwx, *movqi_bwx.
+	(*mov<VEC>): Merge *mov<VEC>_fix, *mov<VEC>_nofix.
+	* config/alpha/constraint.md ("f"): Use NO_REGS when fpu is disabled.
+
+2011-02-24  Richard Henderson  <rth@redhat.com>
+
 	* config/alpha/alpha.md (extendqihi2): Implement for BWX only.
 	(extendqisi2, extendhisi2): Likewise.
 	(extendqidi2): Simplify BWX/non-BWX expansions.

gcc/config/alpha/constraints.md

@@ -32,7 +32,7 @@
 (define_register_constraint "c" "R27_REG"
  "General register 27, function call address")
 
-(define_register_constraint "f" "FLOAT_REGS"
+(define_register_constraint "f" "TARGET_FPREGS ? FLOAT_REGS : NO_REGS"
  "Any floating-point register")
 
 (define_register_constraint "v" "R0_REG"