Fix gcc.target/aarch64/sve2/shracc_1.c for ILP32

2019-10-04  Yuliang Wang  <yuliang.wang@arm.com>

gcc/testsuite/
	* gcc.target/aarch64/sve2/shracc_1.c: Tighten scan-assembler-nots
	to avoid matching scalar code.

From-SVN: r276568

gcc/testsuite/ChangeLog

+2019-10-04  Yuliang Wang  <yuliang.wang@arm.com>
+
+	* gcc.target/aarch64/sve2/shracc_1.c: Tighten scan-assembler-nots
+	to avoid matching scalar code.
+
 2019-10-04  Tobias Burnus  <tobias@codesourcery.com>
 
 	* gfortran.dg/use_without_only_1.f90: Update column num in dg-warning.

gcc/testsuite/gcc.target/aarch64/sve2/shracc_1.c

@@ -24,9 +24,9 @@ SHRACC (uint64_t, 53);
 
 /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */
 
-/* { dg-final { scan-assembler-not {\tasr\t} } } */
-/* { dg-final { scan-assembler-not {\tlsr\t} } } */
-/* { dg-final { scan-assembler-not {\tadd\t} } } */
+/* { dg-final { scan-assembler-not {\tasr\tz[0-9]+\.[bhsd]} } } */
+/* { dg-final { scan-assembler-not {\tlsr\tz[0-9]+\.[bhsd]} } } */
+/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.[bhsd]} } } */
 
 /* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.h, z[0-9]+\.h, #14\n} 1 } } */