ia64.c (ia64_print_operand): Define 'e' as 64-n.

        * config/ia64/ia64.c (ia64_print_operand): Define 'e' as 64-n.
        * config/ia64/ia64.md (rotrsi3): Allow variable rotates; don't
        split until after reload.
        (rotlsi3, rotldi3): New.

From-SVN: r36632

gcc/ChangeLog

+2000-09-25  Richard Henderson  <rth@cygnus.com>
+
+	* config/ia64/ia64.c (ia64_print_operand): Define 'e' as 64-n.
+	* config/ia64/ia64.md (rotrsi3): Allow variable rotates; don't
+	split until after reload.
+	(rotlsi3, rotldi3): New.
+
 2000-09-25  Gabriel Dos Reis  <gdr@codesourcery.com>
 
 	* diagnostic.c (output_last_position): Define.

gcc/config/ia64/ia64.c

@@ -3090,6 +3090,7 @@ ia64_print_operand_address (stream, address)
    C	Swap and print a comparison operator.
    D	Print an FP comparison operator.
    E    Print 32 - constant, for SImode shifts as extract.
+   e    Print 64 - constant, for DImode rotates.
    F	A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
         a floating point register emitted normally.
    I	Invert a predicate register by adding 1.
@@ -3154,6 +3155,10 @@ ia64_print_operand (file, x, code)
       fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
       return;
 
+    case 'e':
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
+      return;
+
     case 'F':
       if (x == CONST0_RTX (GET_MODE (x)))
 	str = reg_names [FR_REG (0)];

gcc/config/ia64/ia64.md

@@ -3858,24 +3858,68 @@
 }")
 
 ;; Use mix4.r/shr to implement rotrsi3.  We only get 32 bits of valid result
-;; here, instead of 64 like the patterns above.
+;; here, instead of 64 like the patterns above.  Keep the pattern together
+;; until after combine; otherwise it won't get matched often.
 
 (define_expand "rotrsi3"
+  [(set (match_operand:SI 0 "gr_register_operand" "")
+	(rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
+		     (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
+  ""
+  "
+{
+  if (GET_MODE (operands[2]) != VOIDmode)
+    {
+      rtx tmp = gen_reg_rtx (DImode);
+      emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
+      operands[2] = tmp;
+    }
+}")
+
+(define_insn_and_split "*rotrsi3_internal"
+  [(set (match_operand:SI 0 "gr_register_operand" "=&r")
+	(rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
+		     (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
+  ""
+  "#"
+  "reload_completed"
   [(set (match_dup 3)
-	(ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" ""))
+	(ior:DI (zero_extend:DI (match_dup 1))
 		(ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
    (set (match_dup 3)
-	(lshiftrt:DI (match_dup 3)
-		     (match_operand:DI 2 "nonmemory_operand" "")))
-   (set (match_operand:SI 0 "gr_register_operand" "") (match_dup 4))]
+	(lshiftrt:DI (match_dup 3) (match_dup 2)))]
+  "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
+
+(define_expand "rotlsi3"
+  [(set (match_operand:SI 0 "gr_register_operand" "")
+	(rotate:SI (match_operand:SI 1 "gr_register_operand" "")
+		   (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
   ""
   "
 {
   if (! shift_32bit_count_operand (operands[2], SImode))
-    FAIL;
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_lowpart (SImode, operands[3]);
+    {
+      rtx tmp = gen_reg_rtx (SImode);
+      emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
+      emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
+      DONE;
+    }
 }")
+
+(define_insn_and_split "*rotlsi3_internal"
+  [(set (match_operand:SI 0 "gr_register_operand" "=r")
+	(rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
+		   (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
+  ""
+  "#"
+  "reload_completed"
+  [(set (match_dup 3)
+	(ior:DI (zero_extend:DI (match_dup 1))
+		(ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
+   (set (match_dup 3)
+	(lshiftrt:DI (match_dup 3) (match_dup 2)))]
+  "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
+   operands[2] = GEN_INT (32 - INTVAL (operands[2]));")
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -3967,6 +4011,24 @@
   "shrp %0 = %1, %1, %2"
   [(set_attr "type" "I")])
 
+(define_expand "rotldi3"
+  [(set (match_operand:DI 0 "gr_register_operand" "")
+	(rotate:DI (match_operand:DI 1 "gr_register_operand" "")
+		   (match_operand:DI 2 "nonmemory_operand" "")))]
+  ""
+  "
+{
+  if (! shift_count_operand (operands[2], DImode))
+    FAIL;
+}")
+
+(define_insn "*rotldi3_internal"
+  [(set (match_operand:DI 0 "gr_register_operand" "=r")
+	(rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
+		   (match_operand:DI 2 "shift_count_operand" "M")))]
+  ""
+  "shrp %0 = %1, %1, %e2"
+  [(set_attr "type" "I")])
 
 ;; ::::::::::::::::::::
 ;; ::