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Commit 661fce82 by Alan Lawrence Committed by Alan Lawrence
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[AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi 

gcc/:

	* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
	TYPES_BINOPV): Delete.
	(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
	AARCH64_SIMD_PATTERN_START.
	(aarch64_init_simd_builtins): Register
	__builtin_aarch64_im_lane_boundsi; use  AARCH64_SIMD_PATTERN_START.
	(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
	AARCH64_SIMD_PATTERN_START.

	* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
	* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.

	* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
	(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
	__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
	vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
	vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
	vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
	vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
	vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.

gcc/testsuite/:

	* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.

From-SVN: r218532
parent 2310e29f
Showing with 70 additions and 23 deletions
gcc/ChangeLog
2014-12-09 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
AARCH64_SIMD_PATTERN_START.
(aarch64_init_simd_builtins): Register
__builtin_aarch64_im_lane_boundsi; use AARCH64_SIMD_PATTERN_START.
(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
AARCH64_SIMD_PATTERN_START.
* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.
* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.
2014-12-09 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/arm_neon.h (__AARCH64_NUM_LANES, __aarch64_lane *2):
New.
(aarch64_vset_lane_any): Redefine using previous, same for BE + LE.
gcc/config/aarch64/aarch64-builtins.c
......@@ -141,10 +141,6 @@ aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_maybe_immediate };
#define TYPES_BINOP (aarch64_types_binop_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_binopv_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_none, qualifier_none };
#define TYPES_BINOPV (aarch64_types_binopv_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_binopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned };
#define TYPES_BINOPU (aarch64_types_binopu_qualifiers)
......@@ -342,9 +338,12 @@ enum aarch64_builtins
AARCH64_BUILTIN_SET_FPSR,
AARCH64_SIMD_BUILTIN_BASE,
AARCH64_SIMD_BUILTIN_LANE_CHECK,
#include "aarch64-simd-builtins.def"
AARCH64_SIMD_BUILTIN_MAX = AARCH64_SIMD_BUILTIN_BASE
+ ARRAY_SIZE (aarch64_simd_builtin_data),
/* The first enum element which is based on an insn_data pattern. */
AARCH64_SIMD_PATTERN_START = AARCH64_SIMD_BUILTIN_LANE_CHECK + 1,
AARCH64_SIMD_BUILTIN_MAX = AARCH64_SIMD_PATTERN_START
+ ARRAY_SIZE (aarch64_simd_builtin_data) - 1,
AARCH64_CRC32_BUILTIN_BASE,
AARCH64_CRC32_BUILTINS
AARCH64_CRC32_BUILTIN_MAX,
......@@ -685,7 +684,7 @@ aarch64_init_simd_builtin_scalar_types (void)
static void
aarch64_init_simd_builtins (void)
{
unsigned int i, fcode = AARCH64_SIMD_BUILTIN_BASE + 1;
unsigned int i, fcode = AARCH64_SIMD_PATTERN_START;
aarch64_init_simd_builtin_types ();
......@@ -695,6 +694,15 @@ aarch64_init_simd_builtins (void)
system. */
aarch64_init_simd_builtin_scalar_types ();
tree lane_check_fpr = build_function_type_list (void_type_node,
intSI_type_node,
intSI_type_node,
NULL);
aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_LANE_CHECK] =
add_builtin_function ("__builtin_aarch64_im_lane_boundsi", lane_check_fpr,
AARCH64_SIMD_BUILTIN_LANE_CHECK, BUILT_IN_MD,
NULL, NULL_TREE);
for (i = 0; i < ARRAY_SIZE (aarch64_simd_builtin_data); i++, fcode++)
{
bool print_type_signature_p = false;
......@@ -974,8 +982,20 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
rtx
aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
{
if (fcode == AARCH64_SIMD_BUILTIN_LANE_CHECK)
{
tree nlanes = CALL_EXPR_ARG (exp, 0);
gcc_assert (TREE_CODE (nlanes) == INTEGER_CST);
rtx lane_idx = expand_normal (CALL_EXPR_ARG (exp, 1));
if (CONST_INT_P (lane_idx))
aarch64_simd_lane_bounds (lane_idx, 0, TREE_INT_CST_LOW (nlanes), exp);
else
error ("%Klane index must be a constant immediate", exp);
/* Don't generate any RTL. */
return const0_rtx;
}
aarch64_simd_builtin_datum *d =
&aarch64_simd_builtin_data[fcode - (AARCH64_SIMD_BUILTIN_BASE + 1)];
&aarch64_simd_builtin_data[fcode - AARCH64_SIMD_PATTERN_START];
enum insn_code icode = d->code;
builtin_simd_arg args[SIMD_MAX_BUILTIN_ARGS];
int num_args = insn_data[d->code].n_operands;
......
gcc/config/aarch64/aarch64-simd-builtins.def
......@@ -397,5 +397,3 @@
VAR1 (BINOPP, crypto_pmull, 0, di)
VAR1 (BINOPP, crypto_pmull, 0, v2di)
/* Meta-op to check lane bounds of immediate in aarch64_expand_builtin. */
VAR1 (BINOPV, im_lane_bound, 0, si)
gcc/config/aarch64/aarch64-simd.md
......@@ -4596,19 +4596,6 @@
[(set_attr "type" "neon_ext<q>")]
)
;; This exists solely to check the arguments to the corresponding __builtin.
;; Used where we want an error for out-of-range indices which would otherwise
;; be silently wrapped (e.g. the mask to a __builtin_shuffle).
(define_expand "aarch64_im_lane_boundsi"
[(match_operand:SI 0 "immediate_operand" "i")
(match_operand:SI 1 "immediate_operand" "i")]
"TARGET_SIMD"
{
aarch64_simd_lane_bounds (operands[0], 0, INTVAL (operands[1]), NULL);
DONE;
}
)
(define_insn "aarch64_rev<REVERSE:rev_op><mode>"
[(set (match_operand:VALL 0 "register_operand" "=w")
(unspec:VALL [(match_operand:VALL 1 "register_operand" "w")]
......
gcc/testsuite/ChangeLog
2014-12-09 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.
2014-12-09 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/vld1_lane-o0.c: New test.
2014-12-09 Alan Lawrence <alan.lawrence@arm.com>
......
gcc/testsuite/gcc.target/aarch64/simd/vset_lane_s16_const_1.c 0 → 100644
/* Test error message when passing a non-constant value in as a lane index. */
/* { dg-do assemble } */
/* { dg-options "-std=c99" } */
#include <arm_neon.h>
int
main (int argc, char **argv)
{
int16x4_t in = vcreate_s16 (0xdeadbeef00000000ULL);
/* { dg-error "must be a constant immediate" "" { target *-*-* } 0 } */
int16x4_t out = vset_lane_s16 (65535, in, argc);
return vget_lane_s16 (out, 0);
}
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