Add support for Loongson 3A2000/3A3000 processor.

gcc/
	* config/mips/gs464e.md: New.
	* config/mips/mips-cpus.def: Define gs464e.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
	gs464e.
	(mips_issue_rate): Add support for gs464e.
	(mips_multipass_dfa_lookahead): Likewise.
	(mips_option_override): Enable MMI, EXT and EXT2 for gs464e.
	* config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e.
	(ISA_HAS_FUSED_MADD4): Enable for TARGET_GS464E.
	(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS464E.
	* config/mips/mips.md: Include gs464e.md.
	(processor): Add gs464e.
	* doc/invoke.texi: Add gs464e to supported architectures.

From-SVN: r265866

gcc/ChangeLog

 2018-11-07  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* config/mips/gs464e.md: New.
+	* config/mips/mips-cpus.def: Define gs464e.
+	* config/mips/mips-tables.opt: Regenerate.
+	* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
+	gs464e.
+	(mips_issue_rate): Add support for gs464e.
+	(mips_multipass_dfa_lookahead): Likewise.
+	(mips_option_override): Enable MMI, EXT and EXT2 for gs464e.
+	* config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E.
+	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e.
+	(ISA_HAS_FUSED_MADD4): Enable for TARGET_GS464E.
+	(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS464E.
+	* config/mips/mips.md: Include gs464e.md.
+	(processor): Add gs464e.
+	* doc/invoke.texi: Add gs464e to supported architectures.
+
+2018-11-07  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* config/mips/loongson3a.md: Rename to ...
 	* config/mips/gs464.md: ... here.
 	* config/mips/mips-cpus.def: Define gs464; Add loongson3a

gcc/config/mips/gs464e.md

+;; Pipeline model for Loongson gs464e cores.
+
+;; Copyright (C) 2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs464e_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs464e_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs464e_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs464e_alu1" "gs464e_a_alu")
+(define_cpu_unit "gs464e_alu2" "gs464e_a_alu")
+(define_cpu_unit "gs464e_mem1" "gs464e_a_mem")
+(define_cpu_unit "gs464e_mem2" "gs464e_a_mem")
+(define_cpu_unit "gs464e_falu1" "gs464e_a_falu")
+(define_cpu_unit "gs464e_falu2" "gs464e_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs464e_arith" 1
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_branch" 1
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_mfhilo" 1
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs464e_alu1 | gs464e_alu2")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs464e_imul3nc" 5
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "imul3nc"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_imul" 7
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "imul,imadd"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_idiv_si" 12
+  (and (eq_attr "cpu" "gs464e")
+       (and (eq_attr "type" "idiv")
+	    (eq_attr "mode" "SI")))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_idiv_di" 25
+  (and (eq_attr "cpu" "gs464e")
+       (and (eq_attr "type" "idiv")
+	    (eq_attr "mode" "DI")))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_load" 4
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "load"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_fpload" 5
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "load,mfc,mtc"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_prefetch" 0
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "prefetch,prefetchx"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_store" 0
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "store,fpstore,fpidxstore"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_fadd" 4
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "fadd,fmul,fmadd"))
+  "gs464e_falu1 | gs464e_falu2")
+
+(define_insn_reservation "gs464e_fcmp" 2
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "fabs,fcmp,fmove,fneg"))
+  "gs464e_falu1 | gs464e_falu2")
+
+(define_insn_reservation "gs464e_fcvt" 4
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "fcvt"))
+  "gs464e_falu1 | gs464e_falu2")
+
+(define_insn_reservation "gs464e_fdiv_sf" 12
+  (and (eq_attr "cpu" "gs464e")
+       (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
+	    (eq_attr "mode" "SF")))
+  "gs464e_falu1 | gs464e_falu2")
+
+(define_insn_reservation "gs464e_fdiv_df" 19
+  (and (eq_attr "cpu" "gs464e")
+       (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
+	    (eq_attr "mode" "DF")))
+  "gs464e_falu1 | gs464e_falu2")
+
+;; Force single-dispatch for unknown or multi.
+(define_insn_reservation "gs464e_unknown" 1
+  (and (eq_attr "cpu" "gs464e")
+       (eq_attr "type" "unknown,multi,atomic,syncloop"))
+  "gs464e_alu1 + gs464e_alu2 + gs464e_falu1
+   + gs464e_falu2 + gs464e_mem1 + gs464e_mem2")
+
+;; End of DFA-based pipeline description for gs464e

gcc/config/mips/mips-cpus.def

@@ -164,6 +164,7 @@ MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED)
 /* MIPS64 Release 2 processors.  */
 MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
 MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
+MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
 MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
 MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
 MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED)

gcc/config/mips/mips-tables.opt

@@ -682,26 +682,29 @@ EnumValue
 Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon) Value(98) Canonical
+Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon+) Value(99) Canonical
+Enum(mips_arch_opt_value) String(octeon) Value(99) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon2) Value(100) Canonical
+Enum(mips_arch_opt_value) String(octeon+) Value(100) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon3) Value(101) Canonical
+Enum(mips_arch_opt_value) String(octeon2) Value(101) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(xlp) Value(102) Canonical
+Enum(mips_arch_opt_value) String(octeon3) Value(102) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(i6400) Value(103) Canonical
+Enum(mips_arch_opt_value) String(xlp) Value(103) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(i6500) Value(104) Canonical
+Enum(mips_arch_opt_value) String(i6400) Value(104) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(p6600) Value(105) Canonical
+Enum(mips_arch_opt_value) String(i6500) Value(105) Canonical
+
+EnumValue
+Enum(mips_arch_opt_value) String(p6600) Value(106) Canonical
 

gcc/config/mips/mips.c

@@ -839,6 +839,9 @@ static const struct mips_rtx_cost_data
   { /* Loongson gs464.  */
     DEFAULT_COSTS
   },
+  { /* Loongson gs464e.  */
+    DEFAULT_COSTS
+  },
   { /* M4k */
     DEFAULT_COSTS
   },
@@ -14615,6 +14618,7 @@ mips_issue_rate (void)
     case PROCESSOR_LOONGSON_2E:
     case PROCESSOR_LOONGSON_2F:
     case PROCESSOR_GS464:
+    case PROCESSOR_GS464E:
     case PROCESSOR_P5600:
     case PROCESSOR_P6600:
       return 4;
@@ -14746,7 +14750,7 @@ mips_multipass_dfa_lookahead (void)
   if (TUNE_SB1)
     return 4;
 
-  if (TUNE_LOONGSON_2EF || TUNE_GS464)
+  if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E)
     return 4;
 
   if (TUNE_OCTEON)

gcc/config/mips/mips.h

@@ -267,6 +267,7 @@ struct mips_cpu_info {
 #define TARGET_LOONGSON_2F          (mips_arch == PROCESSOR_LOONGSON_2F)
 #define TARGET_LOONGSON_2EF         (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
 #define TARGET_GS464		    (mips_arch == PROCESSOR_GS464)
+#define TARGET_GS464E		    (mips_arch == PROCESSOR_GS464E)
 #define TARGET_MIPS3900             (mips_arch == PROCESSOR_R3900)
 #define TARGET_MIPS4000             (mips_arch == PROCESSOR_R4000)
 #define TARGET_MIPS4120             (mips_arch == PROCESSOR_R4120)
@@ -299,6 +300,7 @@ struct mips_cpu_info {
 #define TUNE_LOONGSON_2EF           (mips_tune == PROCESSOR_LOONGSON_2E	\
 				     || mips_tune == PROCESSOR_LOONGSON_2F)
 #define TUNE_GS464		    (mips_tune == PROCESSOR_GS464)
+#define TUNE_GS464E		    (mips_tune == PROCESSOR_GS464E)
 #define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
 #define TUNE_MIPS3900               (mips_tune == PROCESSOR_R3900)
 #define TUNE_MIPS4000               (mips_tune == PROCESSOR_R4000)
@@ -792,7 +794,7 @@ struct mips_cpu_info {
      %{march=mips32r6: -mips32r6} \
      %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
        |march=xlr: -mips64} \
-     %{march=mips64r2|march=loongson3a|march=gs464|march=octeon	\
+     %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \
        |march=xlp: -mips64r2} \
      %{march=mips64r3: -mips64r3} \
      %{march=mips64r5: -mips64r5} \
@@ -910,7 +912,8 @@ struct mips_cpu_info {
 
 #define MIPS_ASE_LOONGSON_EXT_SPEC						\
   "%{!mno-loongson-ext:								\
-     %{march=loongson3a|march=gs464: -mloongson-ext}}"
+     %{march=loongson3a|march=gs464: -mloongson-ext}				\
+     {march=gs464e: %{!mno-loongson-ext2: -mloongson-ext2 -mloongson-ext}}}"
 
 #define DRIVER_SELF_SPECS \
   MIPS_ISA_LEVEL_SPEC,	  \
@@ -1099,14 +1102,16 @@ struct mips_cpu_info {
    'd = [+-] (a * b [+-] c)'.  */
 #define ISA_HAS_FUSED_MADD4	(mips_madd4				\
 				 && (TARGET_MIPS8000			\
-				     || TARGET_GS464))
+				     || TARGET_GS464			\
+				     || TARGET_GS464E))
 
 /* ISA has 4 operand unfused madd instructions of the form
    'd = [+-] (a * b [+-] c)'.  */
 #define ISA_HAS_UNFUSED_MADD4	(mips_madd4				\
 				 && ISA_HAS_FP4				\
 				 && !TARGET_MIPS8000			\
-				 && !TARGET_GS464)
+				 && !TARGET_GS464			\
+				 && !TARGET_GS464E)
 
 /* ISA has 3 operand r6 fused madd instructions of the form
    'c = c [+-] (a * b)'.  */

gcc/config/mips/mips.md

@@ -38,6 +38,7 @@
   loongson_2e
   loongson_2f
   gs464
+  gs464e
   m4k
   octeon
   octeon2
@@ -1174,6 +1175,7 @@
 (include "10000.md")
 (include "loongson2ef.md")
 (include "gs464.md")
+(include "gs464e.md")
 (include "octeon.md")
 (include "sb1.md")
 (include "sr71k.md")

gcc/doc/invoke.texi

@@ -20799,6 +20799,7 @@ The processor names are:
 @samp{i6400}, @samp{i6500},
 @samp{interaptiv},
 @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{gs464},
+@samp{gs464e},
 @samp{m4k},
 @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec},
 @samp{m5100}, @samp{m5101},