re PR rtl-optimization/69032 (ICE: in cfg_preds_1, at sel-sched-ir.c:4809 with…

re PR rtl-optimization/69032 (ICE: in cfg_preds_1, at sel-sched-ir.c:4809 with -fsched-pressure -fsel-sched-pipelining -fselective-scheduling)

gcc/

	PR rtl-optimization/69032
	* sel-sched-ir.c (get_seqno_by_preds): Include both insn and head when
	looping backwards over basic block insns.

testsuite/

	PR rtl-optimization/69032
	* gcc.dg/pr69032.c: New test.

From-SVN: r234219

gcc/ChangeLog

 2016-03-15  Andrey Belevantsev  <abel@ispras.ru>
 
+	PR rtl-optimization/69032
+	* sel-sched-ir.c (get_seqno_by_preds): Include both insn and head when
+	looping backwards over basic block insns. 
+
+2016-03-15  Andrey Belevantsev  <abel@ispras.ru>
+
+	PR target/66660
+	* sel-sched-ir.c (merge_expr): Avoid changing the speculative pattern
+	to non-speculative when propagating trap bits. 
+
+2016-03-15  Andrey Belevantsev  <abel@ispras.ru>
+
 	PR rtl-optimization/63384
 	* sel-sched.c (invoke_aftermath_hooks): Do not decrease issue_more on
 	DEBUG_INSN_P insns. 

gcc/sel-sched-ir.c

@@ -4106,11 +4106,14 @@ get_seqno_by_preds (rtx_insn *insn)
   insn_t *preds;
   int n, i, seqno;
 
-  while (tmp != head)
+  /* Loop backwards from INSN to HEAD including both.  */
+  while (1)
     {
-      tmp = PREV_INSN (tmp);
       if (INSN_P (tmp))
-        return INSN_SEQNO (tmp);
+	return INSN_SEQNO (tmp);
+      if (tmp == head)
+	break;
+      tmp = PREV_INSN (tmp);
     }
 
   cfg_preds (bb, &preds, &n);

gcc/testsuite/ChangeLog

 2016-03-15  Andrey Belevantsev  <abel@ispras.ru>
 
+	PR rtl-optimization/69032
+	* gcc.dg/pr69032.c: New test.
+
+2016-03-15  Andrey Belevantsev  <abel@ispras.ru>
+
 	PR rtl-optimization/63384
 	* g++.dg/pr63384.C: New test. 
 

gcc/testsuite/gcc.dg/pr69032.c

+/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -fsched-pressure -fsel-sched-pipelining -fselective-scheduling" } */
+
+void foo (long long i)
+{
+   while (i != -1)
+     {
+	++i;
+	 __asm__ ("");
+     }
+}