ia64-protos.h (fr_nonimmediate_operand): Declare.

        * config/ia64/ia64-protos.h (fr_nonimmediate_operand): Declare.
        * config/ia64/ia64.c (fr_nonimmediate_operand): New.
        (ia64_override_options): Prevent optimizing division for both
        latency and throughput.
        (rtx_needs_barrier): Handle frcpa.
        * config/ia64/ia64.h (MASK_INLINE_DIV_LAT): New.
        (MASK_INLINE_DIV_THR, TARGET_INLINE_DIV_LAT): New.
        (TARGET_INLINE_DIV_THR, TARGET_INLINE_DIV): New.
        (TARGET_SWITCHES): Add -minline-divide-min-latency and
        -minline-divide-max-throughput.
        (PREDICATE_CODES): Update.
        * config/ia64/ia64.md (extendsidi2): Remove * from f case.
        (zero_extendsidi2): Likewise.  Fix typo in f case insn.
        (extendsfdf2): Add cases for gr<->fr and fr<->mem.
        (extendsftf2): Likewise.
        (extenddftf2): Likewise.
        (fix_trunctfdi2_alts): New.
        (fixuns_trunctfdi2_alts): New.
        (madd*4): Rename from madd*3.
        (divsi3, modsi3, udivsi3, umodsi3): New.
        (divsi3_internal): New.
        (divdi3, moddi3, udivdi3, umoddi3): New.
        (divdi3_internal_lat, divdi3_internal_thr): New.
        (multf3_alts, maddtf4_alts, nmaddtf4_alts): New.
        (recip_approx): New.

From-SVN: r36330

gcc/ChangeLog

+2000-09-11  Richard Henderson  <rth@cygnus.com>
+
+	* config/ia64/ia64-protos.h (fr_nonimmediate_operand): Declare.
+	* config/ia64/ia64.c (fr_nonimmediate_operand): New.
+	(ia64_override_options): Prevent optimizing division for both
+	latency and throughput.
+	(rtx_needs_barrier): Handle frcpa.
+	* config/ia64/ia64.h (MASK_INLINE_DIV_LAT): New.
+	(MASK_INLINE_DIV_THR, TARGET_INLINE_DIV_LAT): New.
+	(TARGET_INLINE_DIV_THR, TARGET_INLINE_DIV): New.
+	(TARGET_SWITCHES): Add -minline-divide-min-latency and
+	-minline-divide-max-throughput.
+	(PREDICATE_CODES): Update.
+	* config/ia64/ia64.md (extendsidi2): Remove * from f case.
+	(zero_extendsidi2): Likewise.  Fix typo in f case insn.
+	(extendsfdf2): Add cases for gr<->fr and fr<->mem.
+	(extendsftf2): Likewise.
+	(extenddftf2): Likewise.
+	(fix_trunctfdi2_alts): New.
+	(fixuns_trunctfdi2_alts): New.
+	(madd*4): Rename from madd*3.
+	(divsi3, modsi3, udivsi3, umodsi3): New.
+	(divsi3_internal): New.
+	(divdi3, moddi3, udivdi3, umoddi3): New.
+	(divdi3_internal_lat, divdi3_internal_thr): New.
+	(multf3_alts, maddtf4_alts, nmaddtf4_alts): New.
+	(recip_approx): New.
+
 2000-09-11  Alexandre Oliva  <aoliva@redhat.com>
 
 	* print-rtl.c (debug_call_placeholder_verbose): New variable.

gcc/config/ia64/ia64-protos.h

@@ -38,6 +38,7 @@ extern int gr_register_operand PARAMS((rtx, enum machine_mode));
 extern int fr_register_operand PARAMS((rtx, enum machine_mode));
 extern int grfr_register_operand PARAMS((rtx, enum machine_mode));
 extern int gr_nonimmediate_operand PARAMS((rtx, enum machine_mode));
+extern int fr_nonimmediate_operand PARAMS((rtx, enum machine_mode));
 extern int grfr_nonimmediate_operand PARAMS((rtx, enum machine_mode));
 extern int gr_reg_or_0_operand PARAMS((rtx, enum machine_mode));
 extern int gr_reg_or_5bit_operand PARAMS((rtx, enum machine_mode));

gcc/config/ia64/ia64.c

@@ -397,6 +397,26 @@ gr_nonimmediate_operand (op, mode)
   return 1;
 }
 
+/* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg.  */
+
+int
+fr_nonimmediate_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (! nonimmediate_operand (op, mode))
+    return 0;
+  if (GET_CODE (op) == SUBREG)
+    op = SUBREG_REG (op);
+  if (GET_CODE (op) == REG)
+    {
+      unsigned int regno = REGNO (op);
+      if (regno < FIRST_PSEUDO_REGISTER)
+	return FR_REGNO_P (regno);
+    }
+  return 1;
+}
+
 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg.  */
 
 int
@@ -3484,6 +3504,12 @@ ia64_override_options ()
   if (TARGET_AUTO_PIC)
     target_flags |= MASK_CONST_GP;
 
+  if (TARGET_INLINE_DIV_LAT && TARGET_INLINE_DIV_THR)
+    {
+      warning ("cannot optimize division for both latency and throughput");
+      target_flags &= ~MASK_INLINE_DIV_THR;
+    }
+
   if (ia64_fixed_range_string)
     fix_range (ia64_fixed_range_string);
 
@@ -3971,6 +3997,11 @@ rtx_needs_barrier (x, flags, pred)
 	case 21: /* flushrs */
           break;
 
+	case 5: /* recip_approx */
+	  need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
+	  need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
+	  break;
+
         case 13: /* cmpxchg_acq */
 	  need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
 	  need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);

gcc/config/ia64/ia64.h

@@ -63,6 +63,10 @@ extern int target_flags;
 
 #define MASK_AUTO_PIC	0x00000200	/* generate automatically PIC */
 
+#define MASK_INLINE_DIV_LAT 0x00000400	/* inline div, min latency.  */
+
+#define MASK_INLINE_DIV_THR 0x00000800	/* inline div, max throughput.  */
+
 #define MASK_DWARF2_ASM 0x40000000	/* test dwarf2 line info via gas.  */
 
 #define TARGET_BIG_ENDIAN	(target_flags & MASK_BIG_ENDIAN)
@@ -85,6 +89,13 @@ extern int target_flags;
 
 #define TARGET_AUTO_PIC		(target_flags & MASK_AUTO_PIC)
 
+#define TARGET_INLINE_DIV_LAT	(target_flags & MASK_INLINE_DIV_LAT)
+
+#define TARGET_INLINE_DIV_THR	(target_flags & MASK_INLINE_DIV_THR)
+
+#define TARGET_INLINE_DIV \
+  (target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR))
+
 #define TARGET_DWARF2_ASM	(target_flags & MASK_DWARF2_ASM)
 
 /* This macro defines names of command options to set and clear bits in
@@ -123,6 +134,10 @@ extern int target_flags;
       N_("gp is constant (but save/restore gp on indirect calls)") },	\
   { "auto-pic",		MASK_AUTO_PIC,					\
       N_("Generate self-relocatable code") },				\
+  { "inline-divide-min-latency", MASK_INLINE_DIV_LAT,			\
+      N_("Generate inline division, optimize for latency") },		\
+  { "inline-divide-max-throughput", MASK_INLINE_DIV_THR,		\
+      N_("Generate inline division, optimize for throughput") },	\
   { "dwarf2-asm", 	MASK_DWARF2_ASM,				\
       N_("Enable Dwarf 2 line debug info via GNU as")},			\
   { "no-dwarf2-asm", 	-MASK_DWARF2_ASM,				\
@@ -2646,6 +2661,7 @@ do {									\
 { "fr_register_operand", {SUBREG, REG}},				\
 { "grfr_register_operand", {SUBREG, REG}},				\
 { "gr_nonimmediate_operand", {SUBREG, REG, MEM}},			\
+{ "fr_nonimmediate_operand", {SUBREG, REG, MEM}},			\
 { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}},			\
 { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}},			\
 { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},	\